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May 15, 2000

Tensilica Processor IP Licensed to Berkeley Wireless Research Center

Santa Clara, Cal., May 15, 2000 … Tensilica Inc., the Santa Clara-based provider of application-specific processor technology, announced today that it has granted a license of its Xtensa Intellectual Property (IP) to the University of California’s Berkeley Wireless Research Center (BWRC).

BWRC will use Tensilica’s Xtensa architecture and Internet-accessed processor generator for its “Two-Chip Intercom (TCI)” Project. The TCI project’s goal is to develop an architectural implementation methodology for wireless protocols as a predecessor towards building a single chip implementation of an ultra-low-power radio (PicoNode). The design methodology is based on multiple levels of abstraction and communication refinement of the levels in a top-down approach.

Professor Jan M. Rabaey, vice chair of the Berkeley Electrical Engineering and Computer Department and co-director of BWRC, said, “We picked the Xtensa architecture because it provides unsurpassed flexibility and extensibility which are crucial to our wireless application. Even more important, however, is Xtensa’s power management capability, an attribute that fits hand-in-glove with next generation wireless applications.”

The TCI system architecture comprises an embedded microprocessor (Xtensa core), reconfigurable logic (FPGA) and dedicated baseband processing network bus architecture on one chip communicating with the RF front-end on a second chip. The top layers of the protocol stack are mapped onto the microprocessor with the lower layers mapped onto reconfigurable hardware and dedicated logic. The processor chip is expected to be taped out during the Summer of 2000.

Bernie Rosenthal, Tensilica’s Vice President of Marketing and Business Development, said “We are delighted to have been selected by BWRC for this challenging project. Not only is it important to be able to configure the processor along with all of the other system-on-chip elements, it’s essential that it meets system requirements precisely due to the critical power constraints of systems. Xtensa ensures both of these needs can be met.”

About Berkeley Wireless Research Center

BWRC’s charter is to provide an environment for research into the design issues necessary to support future wireless communication systems. The research focus is on highly integrated CMOS implementations, which have the lowest possible energy consumption while using advanced communication algorithms. The evaluation of proof of concept prototypes will be made in a realistic test environment.

The Center is a research unit operating as a part of the Electronics Research Laboratory in conjunction with the Department of Electrical Engineering and Computer Science at the University of California, Berkeley. Member companies support the Center with a combination of contributions including involvement of senior level technologists, product, equipment and technology access, and funding to make the Center self sustaining. Corporate members include Cadence, Ericsson, Agilent, Intel, Lucent, ST Microelectronics, and Texas Instruments.

BWRC is located at 2108 Allston Way, Suite 200, Berkeley, CA 94704. BWRC’s URL is bwrc.eecs.berkeley.edu

About Tensilica

Tensilica was founded in July 1997 to address the fast-growing market for application-specific microprocessor cores and software development tools for high volume, embedded systems. Using the company's proprietary Xtensa™ Processor Generator, system-on-a-chip (SOC) designers can develop a processor subsystem hardware design and a complete software development tool environment tailored to their specific requirements in hours.

Tensilica's solutions provide a proven, easy-to-use, methodology that enables designers to achieve optimum application performance in minimum design time. The Company is engaged in research, development, and customer support from its offices in Santa Clara, California, Waltham, Massachusetts, Princeton, N.J., Houston, Texas, Reading, U.K. and Yokohama, Japan.

Tensilica is headquartered in Santa Clara, California (95054) at 3255-6 Scott Boulevard, and can be reached at (408) 986-8000 or via www.tensilica.com on the World Wide Web.

"Tensilica", "Xtensa" and "OSKit" are the trademarks belonging to Tensilica Inc.

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“It is faster and easier to design complex SOCs using Xtensa configurable processors - especially when using the XPRES Compiler - than to hand-code complex SOC design elements in hardware using traditional RTL methods. Plus the Xtensa processors are programmable, so it will be valuable for future products and applications.”

- Katsuhiko Nishizawa, general manager of the IJP Design Department of the Imaging Products Operations Division of Seiko Epson Corporation.