True Application-Specific Embedded Processors Now a Reality For System-on-Chip IC Designs

Santa Clara, Calif., February 15, 1999 … Tensilica Inc., a Santa Clara based start-up, today unveiled the world's first truly configurable and extensible microprocessor architecture and development environment. The new technology enables embedded system designers to rapidly build highly differentiated and optimized synthesizable processor cores for use in ASIC-based products.

Xtensa is the first processor architecture and tool set to bring together a unique combination of technologies to help embedded designers create, verify and implement differentiated processor solutions. Using Xtensa, developers simultaneously tune both application software and processor hardware to meet specific speed, power, and feature goals of their application. Until now, such a closed loop hardware/software design environment has not existed.

Xtensa is targeted at high volume applications like digital cameras, office automation products, wireless communications devices, datacom and telecom protocol processing, and a spectrum of other consumer electronic products.

Tensilica believes that in today's emerging applications, the flexibility in the implementation of the processor subsystem is key. Xtensa provides the ability, through a straightforward method of adding custom functionality to optimize both the hardware and application software simultaneously. The result could be as much as a 20x improvement in the performance of key software algorithms, and performance that can be translated into lower power, higher speed or increased functionality.

According to Tensilica CEO Chris Rowen, "We realized that the vast majority of the processor architectures now being deployed in embedded systems were not originally targeted at today's applications or data types. Starting with a clean sheet of paper, we created a totally new processor architecture, a powerful instruction set and an instruction set extension mechanism. We also facilitated state-of-the-art VLSI implementation, provided a unique application-specific extensibility, and created a totally integrated hardware/software solution.

"The result is," Rowen continued, "a lean, robust, correct by construction processor core design — roughly 25 K gates —that typically operates at speeds equal or better than 250 MHz when implemented in 0.25-micron CMOS. Icing the cake is the design time requirement: we routinely implement substantially new processor designs from configuration to layout in under eight hours."

In developing its Xtensa architecture, the company focused on the application-specific extensibility of the core processor as well as developing effective methods for hardware/software integration and co-design to optimize designs and accelerate time-to-market.

Vinod Dham, President and CEO of Silicon Spice, said "I have surveyed all of the core solutions available from PowerPC to SPARC and MIPS, and found that Tensilica's configurable solution is clearly superior in flexibility and is ideally suited for high performance, low power embedded applications."

According to the Tensilica, today's designers need an advanced RISC-like microprocessor architecture capable of providing all of the performance their system requires without the baggage of unnecessary elements like bulky code or unused functionality. They need control of their processor's source of supply, and they need the ability to easily add functionality to the processor to meet the individual application requirements of their designs. Finally, designers need to be able to create new forms of intellectual property that remain in their control regardless of the manufacturing or distribution strategy employed.

"Tensilica’s Xtensa technology is a major ingredient in ZiLOG’s technology strategy," said Didier Le Lannic, Senior Vice President and General Manager of ZiLOG’s Communications Division. "The Xtensa architecture provides the most flexible and extensible solution for developing microprocessors for embedded applications. We will put this important new technology to work in developing new products for our portfolio of communications devices."

Bernie Rosenthal, Vice President of Marketing and Business Development, said "This means more than just creating another synthesizeable Hardware Description Language (HDL) representation of a processor or providing an easy-to-use, graphical interface to help configure the hardware description. It means building a tightly integrated hardware and software development environment that allows any changes in the hardware to be immediately verifiable and accessible by software tools like C/C++ compilers, assemblers and debuggers.

"Most importantly, "Rosenthal continued, "it means creating a method for those most knowledgeable about the application requirements of a particular system, its designers, to reliably and quickly add specialized coprocessors instructions and interfaces, and have them instantly recognized as "native" by the entire software development tool chain. This is the power of the Xtensa solution."

Xtensa Features

• An easily configurable 32-bit architecture
• High Performance: 250 MHz (typical), 0.25-micron CMOS process
• Low Power: < 0.5 mW/MHz, base configuration in a typical 0.25-micron CMOS process
• Area efficient: base configuration requires ~ 1.0 mm2 using typical 0.25-micron standard cells
• Smaller code: patented instruction encoding methods yield 10-50% better code density than other processor cores
• Optional 16-bit hardware multiplier
• Optional 16-bit DSP unit: fully pipelined 16-bit multiplier and 40-bit accumulator, with dual operand load instructions and address update
• Optional on-chip debug (OCD) module with JTAG-based interface, hardware watchpoints, and 40-bit trace port
• Supports real-time addition of designer-defined instructions using Tensilica Instruction Extension Language (TIE)
• Fully synthesizeable and technology portable
  Each hardware configuration is supported by an automatically generated GNU-based software development toolchain

Targeted Applications

Xtensa is ideal for a broad range of consumer electronics applications such as digital cameras, set-top boxes, and office automation products where superior code density helps minimize memory costs, low power extends battery life, extensibility allows for optimization, and processor performance drives the feature set. In networking applications, the Xtensa processors can serve as distributed compute engines in a multi-channel system-on-chip for packet and protocol processing applications. Adding the powerful 16-bit DSP option to Xtensa makes tightly integrated filtering or servo control functions effective for many modem, wireless or disk drive applications.

Deliverables and Pricing

Tensilica offers customers two delivery options. The standard option provides a firm macro in Verilog or VHDL RTL, and supporting EDA tool scripts, test suite, placement guidelines and the customized software tool chain. The ruggedized option provides a hard macro in the form of a Verilog/VHDL netlist, GDSII using the target semiconductor vendor's cell library, a test suite and the software tool chain.

The company's pricing structure is based upon a licensing fee per instantiated design plus royalties based upon units manufactured. Licensing fees for an individually configured processor implementation and complete software tool environment start at $350,000.

Founders and Key Management

The Company’s founders and key managers are a who’s who of seasoned, successful professionals with experience in the many fields required for the synthesis of the of the company’s unique technology.

Key players include Chris Rowen Ph.D., president and CEO, (Intel, Stanford, MIPS-SGI/Synopsys); Harvey Jones, Chairman (Calma/Daisy/Synopsys); Beatrice Fu, VP Engineering (Intel); Earl Killian, Chief Architect, (MIPS/QED/SGI); Bernie Rosenthal, VP of Marketing & Business Development, (TRW/AMCC/Synopsys); Monica Lam Ph.D., Chief Scientist (Stanford University); and Albert Wang, Chief Engineer (Synopsys).

Venture Financing

The founders provided first round capital, and a second financing round was completed in the second quarter of 1998 with Oak Investments, Worldview Technology, and Foundation Capital.

The Company, in Brief

Tensilica was founded in July 1997 to address the fast growing market for application-specific microprocessor cores and software development tools in high volume, embedded systems. Using the company's proprietary Xtensa Processor Generator, system-on-a-chip (SOC) designers can develop a processor subsystem hardware design and a complete software development tool environment tailored to their specific requirements in hours. Tensilica's solutions provide a proven, easy-to-use, methodology that enables designers achieve optimum application performance in minimum design time. The Company is engaged in research, development, and customer support from its offices in Santa Clara, California, Waltham, Massachusetts, and Tokyo, Japan.

Tensilica is headquartered in Santa Clara, California (95054) at 3255-6 Scott Boulevard, and can be reached at (408) 986-8000 or via the World Wide Web at http://www.tensilica.com

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Notes:

Tensilica, the company’s trademarked name, is synthesized from the words "tensile" (meaning capable of being stretched or extended) and "silica" (a common natural compound in which the element silicon is found).

"Tensilica" and "Xtensa" are the trademarks belonging to Tensilica Inc.
Xtensa technical details appear on the following pages.

The Xtensa Solution and Design Flow

The company's technology embodies a complete embedded microprocessor development solution consisting of a configurable ASIC processor core and all of the requisite software development tools including a C/C++ compiler, assembler, linker, cycle accurate instruction set simulator and code profiler. It allows users to generate all of the optimized custom hardware and software required for achieving true system on chip (SOC) designs economically and quickly.

The keystone of Tensilica's solution is the Xtensa Processor Generator. The Generator makes use of:

• A library of base processor designs that provide for the creation of ultra small and highly efficient new architectures, and
• A closely-coupled function library of pre-verified or designer-defined peripherals.

The output of the Generator includes:

• A GNU-based software tool chain that provides synchronized extensibility to the processor hardware, and
• Efficient RTL synthesis, test suites, and placement information for the very fast creation and integration of the processor cores.

The design flow is simple. Working from a browser-like interface presented on his workstation, the designer chooses the attributes of the processor his application requires. Within about an hour, the Xtensa processor generator provides two critical elements of the design: a tailored HDL microprocessor core that can be combined with a process-specific standard cell library to create and manufacture an SOC design, and a customized GNU C/C++ compiler, assembler, linker, debugger, cycle-accurate simulator, and code profiler.

Before committing to silicon, designers can explore multiple architectures by making area, speed, power and code density design trade-offs based on real time feedback from the generator until the optimal configuration is achieved. Using the appropriate standard cell library along with Tensilica-provided design tool scripts, designers can target their optimized Xtensa processor to the semiconductor process and vendor of their choice.

The Xtensa processor enhances performance and drastically cuts time-to-market for most embedded SOC designs. Not only can its attributes be tuned and extended to match the unique speed and functionality requirements of the application, it is also the superior choice for designs where standards aren’t firmly established, where leveraging the software is critical.

Generator Automatically Produces Development Tools That Match the Processor

The Xtensa software development environment is generated from the same database as the hardware description. This assures correctness and consistency by construction. Processor and software development tool generation use a single set of source files that represent the instruction set. This ensures that designers get an ANSI C compiler, linker, assembler, debugger and instruction set simulator tuned exactly for their hardware. The software toolchain is automatically updated with and can optimize your design using the designer-defined instructions added during the hardware generation process.

Easy to Integrate Designer-Defined Instructions

One of the most important and unique Xtensa features is the real-time development and integration of designer-defined instructions. Using the Tensilica Instruction Extension (TIE) Language, designers can easily and quickly describe a function or set of functions that represent the behavior of an instruction that is not part of the Xtensa base instruction set. The Xtensa processor generator will simultaneously build a hardware representation and generate a C/C++ compiler, assembler, debugger and instruction set simulator with full intrinsic support of the new instructions. This straightforward method of extending the functionality of the processor provides the ultimate degree of control and flexibility in the shortest possible time.

Software Development Tools Based on Industry Standards

The Xtensa software development environment consists of industry-standard GNU tools. These include an ANSI C/C++ compiler, assembler, linker, and debugger. Tensilica has ported and optimized these tools for the Xtensa instruction set architecture and used proprietary techniques to enable various instruction packages based on the particular hardware configuration generated. A graphical user interface to the debug environment is provided via the Data Display Debugger (DDD) utility.

Instruction Set Optimized for Embedded Designs

The Xtensa 32-bit architecture features an instruction set optimized for embedded designs. The base instruction set has a 32-bit ALU, up to 64 general-purpose physical registers, 6 special purpose registers, and 77 instructions (4 loads, 3 stores, 34 branches, 34 arithmetic ops, and 2 miscellaneous instructions). The Xtensa architecture provides optional packages of instruction sets and states for caches, a windowed register file, 16-bit compressed instructions, exceptions, timers, interrupts, debugging, designer-defined instructions, co-processors, integer multiply, and filter DSP unit.

Efficiency characterizes every aspect of the architecture. Xtensa’s patent-pending 16/24-bit encoding with 4-bit register fields reduces the average number of bits per instruction and the static number of instructions required to represent a program. Zero overhead loops can lower branch penalties anywhere the source code calls for a loop to be executed a predetermined number of times. Xtensa utilizes a new type of register window that can cut code size by an additional 10% by reducing the need for register shuffling. Funnel shifts can also save on code size by providing more functionality in a single instruction.

Powerful Debug Capabilities

Xtensa offers a complete debug environment with choices of software break instructions, watchpoint registers and an on-chip debug (OCD) hardware module. The Xtensa instruction set includes BREAK instructions for use by software debug. The designer can monitor the state of a program by adding hardware watchpoints for instruction and/or data address. The OCD module uses a JTAG port and lets the programmer examine the machine state without writing into the machine instruction space for maximum non-intrusiveness. An optional Trace port option allows real-time monitoring of all instruction and data addresses.

Robust Co-Verification Suite

Xtensa’s robust co-verification suite includes a uniform interface for easy access to a cycle-accurate instruction set simulator, a Verilog/VHDL hardware description and an CPLD-based hardware emulator.

The XT-1OOO Device Emulation Kit Provides Opportunity for Early Feedback

The XT1000 Device Emulation Kit is a comprehensive, low cost development tool that uses an Altera CPLD to emulate, in hardware, a specific Xtensa processor configuration. This product enables the developer to evaluate various processor configuration options and start software development and debug early in the design cycle. System designers can specify, implement and debug a new processor configuration, including designer-defined instructions, in just hours.

A predefined external bus interface connects the Xtensa core in the CPLD to the emulation board system resources. The CPLD is configured by downloading the configuration data from a host through a serial port or by copying the configuration data fromprogrammable read only memory located on the emulation board. Optionally, the emulation board can be used asa stand-alone mode in the application of interest. Software development is supported by a resident monitor program, X-MON, that provides communications and debug facilities for the user. An RS232 serial port provides a communications link to the host for downloading and debugging user programs.

Tensilica Tool Support

Tensilica's Xtensa technology supports universally standard EDA tools: Synopsys synthesis; Most popular Verilog and VHDL logic simulators; MOTIVE and Primetime timing analysis tools; and Silicon Ensemble and Apollo place and route tools

Tensilica's Strategic Partners

Tensilica has partnered with leading companies to ensure the highest quality of support for its customers. In alphabetical order, the company's current partners are:

Altera

A leading supplier of Complex Programmable Logic Devices (CPLDs) recognized the value that configurable processors could bring to their users and teamed with Tensilica to create the XT-1000 Emulation Kit for Xtensa processors. Tensilica is a member of the Altera Megafunction Partners Program (AMPP).

Arcadia Design Systems

Supplies datapath placement automation software. Tensilica has embraced a design flow that can utilize the Mustang datapath placement tool for superior results.

Artisan Components

Markets vendor-specific memories, standard cell libraries and I/O cells. Tensilica has proven its core design using Artisan standard cell libraries

Avant!

A worldwide leader in Physical Design Tools and Physical Libraries. Tensilica has exercised implementation flows using Avant! Apollo Layout Tools and Passport libraries

Cadence Design

A leading EDA vendor offering a variety of excellent tools. Xtensa supports logic simulation with Verilog XL and Verilog RC and is collaborating with Cadence to offer support for BuildGates logic synthesis and Silicon Ensemble layout software.

Integrated Systems

Supplier of the industry leading pSOS Real Time Operating System. ISI and Tensilica have partnered to provide a port of pSOS to Xtensa.

Synopsys

A leading provider of design automation software. Tensilica is a member of the IP Catalyst program and supports numerous Synopsys products in the Xtensa design flow including Design Compiler, VCS logic simulation, Vera verification, and Eaglei co-verification.

Virage Logic

A memory cell and generator provider. The Xtensa core has been verified using Virage memory generators

Virtual Silicon Technology

Provides Diplomat standard cell libraries and memory generators for leading semiconductor processes. Tensilica has verified the Xtensa core using Diplomat libraries.

Wind River Systems

A supplier of the industry leading VxWorks Real Time Operating System and Tornado Embedded Software Development Environment. Wind River and Tensilica have joined together to provide a port of the VxWorks RTOS and the Tornado environment to Xtensa.