Articles 2003


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Home > News & Events > Articles > 2003

Articles 2003

Tensilica gets mentioned in a lot of articles. We picked out a few of the best.
12/15/03	How to Improve ROI in SOC Designs - EE Times
12/15/03	Awards Nominees Announced - In-Stat Processor Watch
11/24/03	Breakfast In The Valley: Where Does EDA Go Next? - Electronic News
11/01/03	Tensilica's Better Mousetrap - Electronic Business
10/30/03	Find and Fix Problems Early in the Design Cycle - EDN Magazine
10/27/03	Startup aiming to redefine line card integration - EE Times
09/23/03	Top Influencers in the Semiconductor Industry - EE Times
09/12/03	Eclipse platform eases SoC development - EE Times
09/04/03	Optimizing Multiprocessor Systems - EDN Magaziine
09/01/03	Running RTL power analysis early and often - EE Times Asia
08/27/03	Configurable processors or RTL -- evaluating the tradeoffs - EE Times
08/21/03	Platform-based design: Blocks and buses lead the way - EDN Magazine
07/31/03	SoC interfaces going 'soft' - EE Times
07/18/03	Automated verification of configurable IP blocks - EE Times
07/19/03	In Focus Overview - EE Times
06/23/03	Synthesis and the Embedded CPU - EE Times
06/23/03	Tensilica’s Software Makes Hardware - In-Stat Processor Watch
06/19/03	Tensilica IDE eyes SoC hardware, software design - EE Times Asia
06/16/03	Streamlined CPU cores take center stage - EE Times
06/16/03	IP Cores Crowd SOCs - EE Times
06/05/03	Tensilica Lines Up Co-Design SOC Tool - Electronics Weekly
06/05/03	IP promise still can be kept - EE Times
06/01/03	NEC's New TCP/IP Offload Engine Powered by Tensilica Xtensa - Enterprise Networks & Servers
06/01/03	Configurable Linux for Tensilica Core - Embedded Systems Europe
05/16/03	NEC Boosts TCP/IP Protocol Processing with 10 CPU Cores on One Chip - TechTribes
05/15/03	Analyzing Your Way to a Better System - EDN Magazine
05/14/03	MPEG-4 is accelerated and footprint reduced by use of a configurable processor core - IApplianceWeb
05/09/03	IBM Extends Validation Program to Include Foundry, ASICs - Electronic News
04/08/03	NAB2003: InterVideo Combines MPEG4 Codec with Tensilica Processor - Electronic News
04/04/03	How Tensilica verifies processor cores - EE Times
04/01/03	Survivor: Silicon Valley - Electronic Business
03/27/03	Design reuse expands across industry - EE Times
02/27/03	Panelists urge focus on end customer - EE Times
02/24/03	Vendors debate viable IP business model - EE Times
01/08/03	The New Transistor - EE Times Asia

RECOGNITION

QUOTABLE

“It is faster and easier to design complex SOCs using Xtensa configurable processors - especially when using the XPRES Compiler - than to hand-code complex SOC design elements in hardware using traditional RTL methods. Plus the Xtensa processors are programmable, so it will be valuable for future products and applications.”

- Katsuhiko Nishizawa, general manager of the IJP Design Department of the Imaging Products Operations Division of Seiko Epson Corporation.