SANTA CLARA, CA – February 20, 2006 – Tensilica, Inc. today introduced the Diamond Standard 232L processor core, the lowest power processor capable of running the Linux operating system on the market. With more features, better performance and lower power dissipation than the ARM926EJ-S, Tensilica’s Diamond Standard 232L stands ready to take over new system-on-chip (SOC) designs requiring Linux support.
"Linux has quickly become one of the most popular operating systems for embedded applications," stated Steve Roddy, Tensilica’s vice president of marketing. "With our Diamond Standard 232L processor core, we enable designers to develop new systems with significantly reduced power requirements – essential for handheld mobile applications."
The Diamond Standard 232L was designed specifically for Linux applications, with a fully functioned MMU (memory-management unit), and includes dual 16K, 4-way associative instruction and data caches. The Diamond 232L also includes a strong basic set of digital signal processing instructions including MAC16, MUL16, min/max, sign extend, and NSA (normalized shift amount) instructions. This combination makes the Diamond 232L a very versatile CPU capable of running both complex control applications and mid-range signal processing workloads.
Compared to the ARM926EJ-S processor core, the Diamond 232L consumes less power (delivering longer battery life in handheld applications), while delivering superior general purpose performance (1.3 Dhrystone MIPS per MHz) . And with a physical size less than half that of the ARM926EJ-S, the Diamond 232L costs much less to fabricate.
| ARM 926EJ-S | Diamond 232L | |
|
Max Frequency (0.13u G) worst case, optimized for speed
|
250 MHz | 200-233 MHz |
|
Dhrystone MIPS
|
275 | 300 |
|
Area
|
1.68 mm2 | 0.80 mm2 |
|
mW per MHz (0.13u G) typical conditions
|
0.30 | 0.212 |
|
Zero-overhead looping
|
No | Yes |
|
# Interrupts
|
3 | 15 |
|
Timers
|
No | Yes |
The entire Diamond Standard family is based on Tensilica’s proven Xtensa processor architecture, which is poised to become the number two licensable processor core architecture in the market based on 2006 volume shipments. The Xtensa architecture is a post-RISC-style architecture with native 32-bit data types (operands and ALUs) for the baseline 80+ instructions. Compact 24-bit/16-bit instruction encodings and the ability to do modeless switching between them reduces power consumption and produces 25% to 50% higher code density than standard 32-bit architectures. Register windows for efficient procedure switches provide high performance with low power. The base Xtensa ISA also provides powerful branch instructions and complex bit manipulations.
All Tensilica Diamond Series cores are available with either the native high-performance Tensilica PIF processor interface, suitable for bridging to any on-chip bus (e.g. OCP, CoreConnect) or with an AMBA AHB-Lite interface. SOC designers therefore can choose any common on-chip bus and leverage existing infrastructure and peripheral component sets.
Tensilica’s new Diamond Standard family of processors is available now either direct from Tensilica, or from a roster of ASIC and foundry partners also announced today. See separate news release, or see www.tensilica.com for more details.
Tensilica offers the broadest line of controller, CPU and specialty DSP processors on the market today, in both an off-the-shelf format via the Diamond Standard Series cores and with full designer configurability with the Xtensa processor family. Tensilica’s low-power, benchmark proven processors have been designed into high-volume products at industry leaders in the digital consumer, networking and telecommunications markets. All Tensilica processor cores are complete with a matching software development tool environment, portfolio of system simulation models, and hardware implementation tool support. For more information on Tensilica's patented approach to the creation of application-specific building blocks for SOC design, visit www.tensilica.com.
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