Assigning Tasks to Processors

Mapping tasks to an SOC implementation raises complex issues. Choosing to implement a specific task in a processor, in logic, or in software is a very important decision. There are two guidelines for mapping tasks to processors:

1. The processor must have ample computational capacity to handle the task.
2. Tasks with similar requirements should be allocated to the same processor as long as the processor has the computational capacity to accommodate all of the tasks.

The process of determining the right number of processors cannot be separated from the process of determining the right processor type and configuration. Historically, a real-time computation task is characterized with a “MIPS requirement” – how many millions of execution cycles per second are required. The table below shows a set of tasks with the initial rough estimate of the MIPS requirements for a hypothetical SOC platform that includes 3G wireless connectivity, simultaneous Motion-JPEG compression and decompression (1.2-Mpixel frames at 15 frames/second), audio encoding and decoding, network protocol stack, user interface, and a couple of layered applications.

If all processors provided the same generic performance level, the SOC would need to provide more than 11 billion instructions/second of computing capacity—a job for at least four Intel Pentium-class processors that would consume more than 200 Watts. However, different processors can have very different computational characteristics. A control task is likely to need substantially more cycles if it’s running on a simple DSP than if it’s running on a RISC processor. A numerical task is likely to need more cycles running on a RISC CPU than if it’s running on a DSP. The advantage of using different processors for different tasks is the ability to better match the processors’ performance capabilities to the tasks’ needs. The disadvantage of mixing RISC processors and DSPs is the added burden of working with more than one set of software development tools. This is why many multiple processor SOC designs contain processors from no more than two different companies—to reduce the number of different software tools that must be learned.

Configurable processors can be modified to provide much higher performance than general-purpose RISC processors for specific tasks. Optimizing the configurable processor for a specific application can reduce the number of cycles required to execute a task by 10x to 50x. These optimizations often allow configurable processors to be used for tasks that could never be accomplished by a general-purpose RISC processor core running at any realistic clock rate, and previously had to be designed as blocks of hardware using Verilog or VHDL. The table below revisits the simple allocation of tasks in the table above showing a hypothetical acceleration for each task that reduces the MIPS requirements by using a processor specifically configured for that task.

For more information, get a copy of the book “Engineering the Complex SOC: Fast, Flexible Design with Configurable Processors,” by Chris Rowen, published by Prentice Hall.