Building System Models for Design Space Exploration

One of the most common Electronic System Level design applications is the building of system models for an architecture in order to carry out design space exploration. These models are created using ad-hoc modeling environments based on C/C++ or SystemC, or using a variety of ESL tools from commercial vendors. For a processor-centric design, incorporating instruction set simulation (ISS) models of processors and running real target application code on these models is important. In addition, models of other components, such as memories, connectors, buses, queues, arbiters, routers and other IP blocks is often desirable. The use of transaction-level, as opposed to pin-level, interfaces between models speeds the execution of the user’s simulation models. A number of different modelling and design space exploration strategies are possible.

We assume that the application has been partitioned into one or more tasks. In addition, a basic set of processor configurations has been selected (e.g. from our Tensilica Diamond cores) and/or created (for example, using our XPRES tool. A system architect wishing to build a system model now has several possibilities:

1. Tensilica provides the XTMP single- and multi-processor modeling environment. XTMP is a set of libraries and application development capabilities that allow the creation of system-level models using processors, memories, connectors, queues and user-defined models for hardware accelerators and peripheral blocks. XTMP can be used with either C or C++ and a variety of threading libraries including SystemC. Users construct XTMP models of their system and identify compiled tasks to be loaded on the various processor(s). A number of profiling and processor tracing capabilities allow XTMP models to be used for design space exploration and system-level debugging. XTMP uses a transaction-level model interface that can be interfaced to other system level models and allows execution efficiency.
2. XTMP models can be interfaced to SystemC system models using a number of methods including building model wrappers. In addition, Tensilica is working to improve the SystemC compatibility of its modelling environments. This allows user and other third-party IP models written in SystemC to be integrated into a complete system model.
3. XTMP has been interfaced and integrated to a number of different commercial ESL SOC architecture assembly, simulation and analysis tools. Most of these are based on SystemC. This is done by building appropriate model wrappers. Such tools allow the integration of other third-party IP models and a number of different capabilities for performance monitoring, analysis and optimisation.

System modelling continues to develop. The Open SystemC Initiative (OSCI) is working on advanced transaction level modelling standards to allow better model interoperability. The Tensilica transaction-level models can be interfaced and transformed to work with such standards as they evolve.