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Viterbi Example
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Add Tailored Instructions for a 250x Speed Improvement
Viterbi decoding also comes from GSM cellular telephony. GSM employs Viterbi decoding to pull information symbols out of a noisy transmission channel. This decoding scheme employs “butterfly" operations consisting of 8 logical operations (4 additions, 2 comparisons, and 2 selections) and uses 8 butterfly operations to decode each symbol in the received digital information stream.
Viterbi Butterfly Operation Requires Lots of Cycles in Most RISC Processors and Even DSPs
Typically, RISC processors need 50 to 80 instruction cycles to execute one Viterbi butterfly although the stock Xtensa processor only needs 42 instructions. A high-end VLIW DSP is much better than most processors for Viterbi decoding because it only requires 1.75 cycles per Viterbi butterfly. However, high-end VLIW DSPs are very expensive and consume a lot of power.
Add a Viterbi Butterfly Instruction Using TIE
Tensilica’s TIE (Tensilica Instruction Extension) language allows a designer to add a Viterbi butterfly instruction to the ISA including the corresponding pipeline hardware shown in the figure below (approximately 11,000 gates), and the processor’s configurable 128-bit I/O bus to load data for 8 symbols at a time.
Speed Up by 250X
These additions result in an average Viterbi butterfly execution time of 0.16 cycles per butterfly (a 250x speed improvement) for the augmented Xtensa processor – much better than even the high-end VLIW DSP.
