The What, Why and How of Configurable Processors
How to Avoid the Traps and Pitfalls of SOC Design
A Processor & DSP Selection Checklist
Get your ASICs and SOCs off the Bus!
Processor Configuration with Chris Rowen
How can a processor provide equivalent power savings to an RTL block? Don’t processors, by definition, use more power? Not Tensilica’s Xtensa processors.
Tensilica has automated the insertion of fine-grain clock gating for every functional element of the Xtensa processor including functions conceived of and created by the designer. Clock gating is a very effective power reduction technique that turns off the power to parts of the logic that are not in use on a particular clock cycle. Because automatic insertion of clock gating is only available for restricted RTL design coding styles, manual, error-prone post-layout tuning of clock circuits is often required for standard RTL design.
Tensilica’s Xtensa LX2 processor delivers direct I/O capability, using ports and queues, that is equivalent to RTL design, eliminating the wasted power of moving data into and out of conventional DSP/RISC cores using Load/Store operations.
The Xtensa LX2 processor’s architecture dramatically lowers power consumption in large configurations with many designer-defined functions. But even without designer modification, the Xtensa LX2 processor is designed to use power very efficiently. The minimum configuration of the Xtensa LX processor dissipates a miserly 38 micro-W/MHz in a representative 130 nm process technology. By comparison, the smallest member of the ARM synthesizable processor family, the ARM7TDMI-S, burns 110 micro-W/MHz in 130 nm technology – twice the power consumption of the Xtensa LX.
See our Synopsys User’s Group (SNUG) Presentation and Paper on “Implementing Power Management IP for Dynamic and Static Power Reduction in Configurable Microprocessors using the Galaxy Design Platform at 130nm"
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The above chart shows that power consumption is minimized with Xtensa LX2.
