Low Power

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Getting Low Power from a Processor

How can a processor provide equivalent power savings to an RTL block? Don’t processors, by definition, use more power? Not Tensilica’s Xtensa processors.

Fine-Grain Clock Gating - Automatically

Tensilica has automated the insertion of fine-grain clock gating for every functional element of the Xtensa processor including functions conceived of and created by the designer. Clock gating is a very effective power reduction technique that turns off the power to parts of the logic that are not in use on a particular clock cycle. Because automatic insertion of clock gating is only available for restricted RTL design coding styles, manual, error-prone post-layout tuning of clock circuits is often required for standard RTL design.

Direct I/O Eliminates Wasted Power on the Bus

Tensilica’s Xtensa LX processor delivers direct I/O capability, using ports and queues, that is equivalent to RTL design, eliminating the wasted power of moving data into and out of conventional DSP/RISC cores using Load/Store operations.

Designed to Use Power Very Efficiently From the Start

The Xtensa LX processor’s architecture dramatically lowers power consumption in large configurations with many designer-defined functions. But even without designer modification, the Xtensa LX processor is designed to use power very efficiently.

The chart below illustrates how low the power is for Xtensa LX - from the smallest configuratio to one of the largest, our high-performance Diamond Standard 570T core.

Xtensa LX Configuration Description Power (TSMC 45 GS, Low-Power flow)
Smallest - with local instruction and data RAM interfaces, full clock gating
 0.009 mW/MHz
Large Diamond 570T
 0.034 mW/MHz

The above chart shows how low the power consumption is with Xtensa LX.

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