Methodology
I/O Throughput
White Papers
The What, Why and How of Configurable Processors
How to Avoid the Traps and Pitfalls of SOC Design
A Processor & DSP Selection Checklist
Get your ASICs and SOCs off the Bus!
Videos
Processor Configuration with Chris Rowen
Getting RTL I/O Throughput from a Processor
The Xtensa LX2 processor’s true breakthrough in I/O is the capability to add designer-defined ports and queues, which allow the processor to communicate as fast and as flexibly as RTL blocks.
Ports (GPIOs) are wires that directly connect two Xtensa LX2 processors or an Xtensa LX2 processor to external RTL. Port connections can be arbitrarily wide, allowing wide data types to be transferred easily without the need for multiple load/store operations. As many as one million signals (1024 1024-bit-wide ports) can be used, and while this is an outrageous number, far exceeding the performance demands of real systems today (providing 350 terabits/sec. of direct data flow per processor in a 130 nm CMOS process), this clearly demonstrates that old notions of the I/O bottlenecks inherent in a processor-based solution are now obsolete.
Designers can add ports and queues to get virtually limitless I/O
While ports are ideal to quickly convey control and status information, Queues (FIFO interfaces) provide a high-speed mechanism to transfer streaming data. Input queues and output queues operate to the programmer’s viewpoint like traditional processor registers - with the notable exception that data is always available without the need to load or store the data before and after computation.
Queues can sustain data rates as high as one transfer every clock cycle or over 350 Gbits/sec for each queue added to an Xtensa LX2 processor. Custom instructions can perform multiple queue operations per cycle, perhaps combining inputs from two input queues with local data and sending the computed values to two output queues. The high bandwidth and low control overhead of queues allows the Xtensa LX2 processor to be used in applications with extreme data rates.
Automated - Easy to Add to Your SOC Design
Ports and Queues specified by the designer using only one instruction and are automatically added to the Xtensa LX2 processor and are 100% fully modeled by Tensilica’s Xtensa Processor Generator. The full behavior of the port or queue, just like any other modification made to the Xtensa LX2 processor, is automatically reflected in the custom software development tools, instruction set simulator, bus functional model and EDA scripts - in about an hour. And because it’s automated using Tensilica’s patented technology, it’s pre-verified and correct by construction - no need to re-verify the processor.
