ESL Design

There are two ways to achieve the time-saving advantages of ESL design using Tensilica’s approach to SOC design. You can run your C/C++ program through our XPRES Compiler, which will automatically configure an Xtensa LX processor for you. Or you can extend a basic processor configuration by writing your own processor instructions using TIE (the Tensilica Instruction Extension language) to extend the processor. Either way, Tensilica guarantees the results will be correct by construction, saving you valuable verification time.
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C/C++ Design

With Tensilica’s XPRES Compiler, you start with your algorithm, written in C or C++, and the XPRES Compiler analyzes it and automatically figures out a number of Xtensa LX processor configurations that provide various area/performance trade-offs, so that you can pick the best trade-off for your application.
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Multiple Processor Design

Find out why most of Tensilica’s customers achieve their aggressive performance goals by using multiple processor cores in their SOC designs. We have a lot of multiple processor design experience to share with you.
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Optimize with TIE

Xtensa processors can be optimized using our TIE (Tensilica Instruction Extension) language, which allows you to add powerful new processor instructions, execution units, designer-defined register files and designer-defined state variables. The TIE Compiler ensures that all additions and extensions are correct-by-construction. It also generates, in minutes, all of the necessary files needed to customize the software tool chain, extend the instruction-set simulator and C modeling environment, estimate the actual hardware cost and maximum clock rate, and enable formal verification.
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Speed RTL Design

Until now, demanding tasks had to be hard coded in RTL to get the speed required. General-purpose processor cores and DSPs just aren’t fast enough for tasks that require heavy lifting. That’s why SOC design teams have resorted to designing large blocks of RTL in the past to get the performance they needed. However, designing millions of gates in RTL takes too long, is too hard to verify, and can’t be changed once the chip is fabricated. These liabilities slow the design cycle and increase design risk.

Now there’s a real alternative to RTL design. You can use configurable, extensible processors instead of RTL to speed your design and to add the flexibility needed to adapt to changing standards or product requirements without incurring a silicon re-spin. Tensilica’s Xtensa processors provide both the I/O throughput and the computational performance previously only possible through manual RTL design. Take this tour and find out how you can speed your design process.
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EDA Design Flow

Because the Xtensa Processor Generator creates HDL descriptions of custom processors in VHDL or Verilog, Xtensa processor cores easily fit into standard EDA design flows. The Xtensa Processor Generator creates a fully synthesizable processor core in about an hour. In addition, the Xtensa Processor Generator provides modeling and EDA tool files that are custom tailored to your exact configuration.
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System Modeling

The Xtensa Modeling Protocol (XTMP) allows rapid assembly of system-level simulations of one or more Xtensa processors and various memories and building blocks. With the Xtensa ISS and XTMP, designers can rapidly build and simulate complete SOC subsystems using multiple, heterogeneous Xtensa processors.Both the standalone Xtensa ISS and all XTMP simulation models are SystemC compatible.
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