Many SOCs are designed with multiple Xtensa processors. One of our customers has designed a chip that employs almost 200 processors. Whether they’re homogeneous arrays of processors performing high-throughput communications tasks or a group of heterogeneous processors performing different tasks in an image processing chain, the allocation of performance among all of the tasks in a SOC design is much easier with multiple Xtensa processors than with just one control processor and multiple blocks of logic.

The Benefits of Multiple Processor Design

There are several advantages to using multiple processors as SOC task building blocks. One of the biggest is that processors are inherently programmable, so functional changes can be made to the chip’s operation using firmware after the chip design is finished and even after the chip has been fabricated. Complex state machines can be implemented in firmware running on the processors, greatly reducing verification time.

In addition, a multiple-processor-based design approach promotes the flexible sharing and reuse of on-chip memories while reducing the overall amount of memory needed.

Design with multiple processors facilitates system modeling with instruction-set simulators, which are much faster and more efficient than RTL-based system simulation.

Additionally, by employing multiple processors in SOC designs, it’s easier to develop one SOC that works for several different related products, such as different models of digital cameras, cell phones or printers.

One of the hidden benefits of spreading tasks across multiple processors is that breaking the SOC’s overall task into smaller subtasks. Spreading these subtasks across multiple processors actually speeds the process of writing and debugging the required software. See Jack Ganssle’s article, "Subtract Software Costs by Adding CPUs."

The Key Questions for Multiple Processor Design

This section shares some of the answers to these key questions. How do you use multiple processor cores to develop an SOC? How do you partition your design to take maximum advantage of multiple processors? How do you take a task that you know cannot be run on a conventional processor core meeting your power, area, and performance goals, and transform an Xtensa processor so that it has the I/O throughput, computational parallelism, and low power of a hand-crafted state-machine driving an RTL datapath? How do you manage the software among all the processors? How do you connect them and manage communication in the hardware?

At Tensilica, we’ve been working with our customers and can help you efficiently design with multiple Xtensa processors. For more information, read all the subsections in this section and get a copy of the book “Engineering the Complex SOC:  Fast, Flexible Design with Configurable Processors,” by Chris Rowen, published by Prentice Hall.