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METHODOLOGY

  Overview

  ESL Design

  C/C++ Design

  Speed RTL Design

  Multi Processor Dsgn

  + Design Process

  + Modeling

  + Partitioning

  + Task Assignments

  + Interconnect

  + Communications

  + Interfaces

  Low Power Design

  Optimized with TIE

  EDA Design Flow

  System Modeling

Modeling

Early System Modeling

If the tasks can be represented as algorithms expressed in a programming language, such as C, the architect should consider early system modeling. At this stage, tasks have not been allocated to processors, and communications among tasks are still expressed abstractly, either through message passing or shared memory. This early modeling will verify the functionality of the set of tasks and it can measure the size, type and number of messages or data operands transferred between tasks.

In theory, an early abstract system simulation model can serve as the basis for sizing the computational demands of each task. This information is not exact, but it can yield important insights into both computational and communications hot spots.

Using system simulation throughout the design process has two advantages: 1) an early start to simulation provides insight into bottlenecks, and 2) the model’s role as a performance predictor gradually evolves into a role as a verification test bench. To test a subsystem, a designer replaces the subsystem’s high-level model with a lower-level implementation model.

Tensilica’s Xtensa Modeling Protocol (XTMP)

Tensilica’s XTMP is an API and runtime environment for rapid multi-processor description and analysis. It provides a unified method to describe system organization, communications mechanisms, and application software, helping the design team quickly move from back-of-the-envelope estimates to accurate simulation. XTMP employs its own simulation engine and generates SystemC-compatible models.

XTMP can be used for simulating homogeneous and heterogeneous multiple processor subsystems as well as complex uniprocessor architectures. The XTMP API allows system designers to write customized, multithreaded simulators to model complex systems. Designers can instantiate multiple similar and dissimilar Xtensa processor cores and use the XTMP API to quickly connect these simulated processor cores to memories, peripherals, interconnects, and designer-defined subsystems.

More details about XTMP and a simple XTMP example are shown in Chapter 4 of the book “Engineering the Complex SOC: Fast, Flexible Design with Configurable Processors,” by Chris Rowen, published by Prentice Hall.

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“We selected Tensilica’s Xtensa processor for its ability to help us achieve our goal of developing innovative-multi-gigabit, lower-power mmWave communications products. By optimizing the Xtensa processor into a tailored processor core, this enables our products to attain the performance these wireless applications demand.”

Kumar Mahesh, Manager of MAC and Software Design for SiBEAM, Inc.