Interfacing with Non-Processor Building Blocks
Processors cannot fulfill every function on a
SOC, so they must interface with memories, I/O
interfaces, and RTL blocks. Off-chip memories – often
non-volatile – hold boot code that allows
the processors to initialize. On-chip memories,
closely coupled to the processor pipeline, hold
the instruction and data sets most immediately
required by the processor’s application code.
Other RAMs hold shared data across tasks or serve
as input and output buffers. Even on-chip ROMs
make economic sense in some SOCs. These guidelines
may help designers take better advantage of RAMs:
- Off-chip RAM is much cheaper than on-chip RAM,
at least for large memories.
- Use caches and shared memories when on-chip
RAM requirements are uncertain.
- Perform a system-performance sanity check by
assessing memory bandwidth. Look at the memory-transfer
requirements of each task to ensure that the
processor’s local memories can handle the
traffic.
Watch for contention latency in memory access.
Increase memory width or increase the number of
memories that can be active to overcome these bottlenecks.
Pay particular attention to tasks that must move
data from off-chip memory, through the processor,
and back to off-chip memory; these tasks can quickly
consume all available bandwidth.
Many I/O peripheral use industry-standard communications
connections that have quite modest bandwidth demands
and put no special burden on interconnect structure
or software device drivers. High-bandwidth interfaces – such
as LAN and WAN network connections and video ports – present
more of a design challenge. There are two approaches
to efficient integration of high-bandwidth I/O:
- Use an autonomous DMA (direct memory access)
engine.
- Couple the I/O interface tightly to a processor,
allowing the function to be software controlled.
Even though processors make a potent alternative
to hardwired logic blocks, often RTL blocks have
already been designed and verified, so reuse them
if appropriate. Two interface mechanisms to RTL
blocks include:
- Map the hardware block’s registers into
local memory space, which makes the hardware
block look much like an I/O device, and makes
the controlling software look much like a standard
device driver.
- Extend the instruction set to directly stimulate
hardware functions. With configurable and extensible
processors, the designer can specify new processor
instructions that take hardware block outputs
as instruction-source operands and use hardware
block inputs as instruction-result destinations
(thus avoiding the use of intermediate registers
and greatly accelerating the task by eliminating
I/O overhead).
For more information, get a copy of the book “Engineering
the Complex SOC: Fast, Flexible Design with Configurable
Processors,” by Chris Rowen, published
by Prentice Hall.
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