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METHODOLOGY

  Overview

  ESL Design

  C/C++ Design

  Speed RTL Design

  + Performace

  + I/O Throughput

  + No State Machines

  + GSM Codec Example

  + Viterbi Example

  + MPEG-4 Example

  + Low Power

  + Design Faster

  Multi Processor Dsgn

  Low Power Design

  Optimized with TIE

  EDA Design Flow

  System Modeling

GSM Audio Codec Example

Use Simple Configuration Options to Optimize Performance

This first example, from the cellular telephone world, involves the GSM audio codec used in cell phones. Profiling the codec code using an unaugmented RISC processor revealed that out of the more than 200 million processor cycles, 80% of the cycles were devoted to executing multiplications.

The simple addition of a hardware multiplier, therefore, would substantially accelerate this software. The Xtensa processor offers a multiplier as a configuration option.

The addition of a hardware multiplier reduces the number of cycles needed to execute the GSM audio codec code from 204 million cycles to 28 million cycles, a 7x improvement.

Adding a few more gates to the processor pipeline by selecting a multiplier/accumulator rather than a multiplier further reduces the number of cycles needed to execute the codec code to 17.9 million cycles, an 11x improvement over the original code.

By providing a wide range of configuration options, designers can profile the code to rapidly explore a design space and make informed trade-offs.

Configuration options coupled with code profiling allow a SoC designer to rapidly explore a design space and to make informed cost/benefit decisions for various design approaches.

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“We selected Tensilica’s Xtensa processor for its ability to help us achieve our goal of developing innovative-multi-gigabit, lower-power mmWave communications products. By optimizing the Xtensa processor into a tailored processor core, this enables our products to attain the performance these wireless applications demand.”

Kumar Mahesh, Manager of MAC and Software Design for SiBEAM, Inc.