ESL Design

Methodology » ESL Design

Design at a Higher Level for More Productivity


While it seems almost every EDA company has a slightly different definition and product offering around ESL (electronic system level) design, all of these solutions are about starting in a high-level language, like C, and avoiding writing tons of time-consuming, hard-to-verify RTL.

Tensilica's customizable DPU technology enables this paradigm shift by empowering SOC designers to implement greater portions of their overall SOC with C-programmable efficient processors. A tuned, optimized DPU running optimized C code delivers the higher level of design productivity and design flexibility that today's design teams need.

In addition to offering finely tailored processors as an alternative to High Level Synthesis techniques offered by many EDA companies, Tensilica also supports ESL design through our offering of various high level models, and support of several 3rd party virtual prototyping tools.

Tensilica offers the widest array of modeling choices of any provider of licensable microprocessor or DSP (digital signal processing) IP cores. IC designers  can use Tensilica's fast, instruction-accurate functional models for early design exploration and software development, more detailed pipeline accurate models with TLM interfaces connected to other devices modeled in SystemC, or cycle-accurate pin-level SystemC models to verify the interconnection of the processor with tightly coupled hardware blocks via Verilog simulation.

See our hardware/software development tools section for more details on these powerful tools.

Tensilica has partnered with all of the leading vendors of ESL modeling tools to enable complete SOC modeling of designs that use Tensilica DPUs. These include:

  • Carbon Design Systems - Tensilica's processor models are integrated into the Carbon SoC Designer virtual platform, enabling designers to perform implementation-accurate architectural analysis and pre-silicon firmware development.
  • Imperas - Fast functional, instruction-accurate models of Tensilica's DPUs can run on Open Virtual Platform (OVP) based virtual platforms.
  • Synopsys - Tensilica's automatically generated models are compatible with Synopsys' Innovator virtual platform development tool as well as the CoWare Platform Architect tool. Tensilica also worked with VaST, another Synopsys acquisition, so customers can use the VaST CoMET and METeor tools - together with virtual processor, bus and peripheral models - to develop virtual system prototypes.
  • Wind River - Tensilica's DPU models work with Simics (from acquisition of Virtutech) hardware virtualization tools.

 

 

 

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