EDA Design Flow for Tensilica's Processors

Methodology » EDA Flow

Fully Compatible With Standard EDA Design Flows

Tensilica's dataplane processors (DPUs) easily fit into standard EDA design flows. The Xtensa Processor Generator creates a fully synthesizable RTL design in about an hour. In addition, the Xtensa Processor Generator provides modeling and EDA tool support custom tailored to your exact configuration.

EDA Tool Support

The following standard EDA tools are fully supported by the Xtensa Processor Generator and by the Tensilica post-sales support team.

Function EDA Vendor Tool
ESL Design Synopsys Platform Architect, Innovator
ESL Design Carbon Design Systems SoC Designer virtual platform environment
ESL Design Imperas Open Virtual Platform
ESL Design Wind River Simics
Logic Synthesis* Synopsys, Cadence, Magma
 Design Compiler, RTL Compiler. Talus
Logic Simulation Cadence, Mentor Graphics, Synopsys Incisive, Questa, VCS
Timing Analysis Synopsys Primetime
Place & Route* Cadence, Synopsys, Magma
 SOC Encounter, IC Compiler, Talus
3D-Extraction* Cadence QRC
Power* Synopsys Power Compiler
Test* Synopsys DFT Compiler
Formal Verification* Synopsys, Cadence Formality, Conformal
Emulation EVE Zebu
FPGA Synopsys Synplify Pro

* Includes automated scripted support.

Works with MATLAB, Too

Are you using MATLAB to figure out the best algorithm for your design? You can use your MATLAB output in your Tensilica flow. See our notes: Linking MATLAB to the Tensilica Instruction Set Simulator (ISS) and Emulating TIE Instructions and TIE-Based Functions in MATLAB.

System Exploration and Modeling

The earliest phases of any SOC design are the system analysis, exploration and modeling phases. Tensilica provides unparalleled support for a variety of system modeling strategies.

For architects doing C-level simulations, the Xtensa Modeling Protocol Instruction Set Simulator (ISS) and XTMP simulators are C-callable executable programs that can, and have been successfully, integrated into larger SoC or system simulation environments.

For architects interested in SystemC simulation, the XTensa SystemC (XTSC) performs similar functions to XTMP. See our System Modeling section for more details.

Additionally, designers can use tools from Synopsys, Carbon and Wind River with Xtensa and Diamond Standard processors for SystemC ESL design.

Hardware Implementation: Automated, Optimized EDA Scripts

Designers can use the fully automated reference hardware design flow provided with the Xtensa processor or blend elements of the automatically generated scripts into an existing ASIC or COT design flow.

Tensilica’s Xtensa processor generator automatically creates customized scripts for logic synthesis, physical synthesis, place and route, test insertion, power simulation and optimization, and 3D extraction and timing analysis.

In addition, Tensilica provides a utility that can automate the execution of a variety of implementation strategies – enabling the designer to try numerous alternatives and pick the optimal physical implementation for the specific SOC design. This utility captures information about the library, constraints and optimization switches - variables that affect the synthesis, physical synthesis and layout. Numerous design constraints and environments can be specified, including both high-level optimization choices and fine-grained, detailed switch settings. This implementation-specific information is then converted into tool specific scripts used to drive tools from a variety of EDA vendors [see table above]. It can also be used to help choose from different silicon foundry or cell library options.

Verification

PreVerified Cores

All Xtensa processor cores are pre-verified before they are delivered to you from the Xtensa processor generator, so you can avoid the lengthy verification process required by hand-crafted RTL blocks. For more information on the overall processor verification process, read "How Tensilica Verifies Processor Cores."

Integration

Tensilica uses an extensive set of simulation monitors within the Xtensa processor design. To facilitate the integration of the Xtensa processor within the larger SOC design, we include a subset of these monitors for your SOC simulation environment.

Tensilica uses System Verilog to implement the monitors.  These monitors facilitate integration of the Xtensa RTL model into your testbench. The monitors included with each processor download are valuable because they check for protocol violations of the hardware attached to the Xtensa processor and provide trace and PC monitoring capabilities. The monitors print informative debug messages whenever violations occur, making the monitors a powerful tool for debugging your SOC hardware.

Custom Instructions

All designer-defined TIE instructions are correct-by-construction using Tensilica’s patented processor generation technology.  What you specify in the single-source TIE description is what will be implemented automatically, correctly and consistently in hardware, software tools and models.

To further assure that what you specified is what you intended to create, the Xtensa processor generator automatically creates a self-checking testbench for each Xtensa processor which incorporates the ISS and the processor hardware RTL. This testbench enables you to run and verify your testbench C code on the real hardware description to fully exercise your designer-defined TIE instructions and ensure that your specification of the TIE instruction meets your system requirements.

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