The New SOC Design Process

SOC design using multiple processors is a technique that provides a new way to speed the SOC design process. The process starts with the fundamental inputs – interface and functional requirements of the chip. This diagram overviews the new flow:

The New SOC Design Process

This flow relies on several important principles. First, early system-level simulation is a key tool for providing detailed insight into the function and performance issues for a complex SOC architecture. Second, the design team can quickly learn various cost and performance tradeoffs by doing rapid incremental refinement from initial implementation guesses into final application, processor configuration, memory, interconnect and input/output implementations. Third, dividing the system software into smaller, processor-sized tasks greatly improves coding efficiency.

Importantly, this new design flow does not make new demands on total design resources or mandate new fundamental engineering skills. Tensilica’s experience with a large number of design teams suggests that both traditional RTL designers and embedded software developers can be comfortable and effective in developing new processor configurations using automated processor-generation tools. Familiarity with C and Verilog are both useful foundations for the effective and efficient use of the processor-centric SOC design method.

Essential Phases of This Flow

The new flow highlights five basic steps:

1. Functional System Modeling – Develop a C or C++ program that captures the most performance-demanding or complex system activities. Only those features that are expected to drive key design decisions need be modeled at this stage.
2. Function-to-Architecture Mapping – Compile and run the core task or tasks on the baseline processor to establish a reference performance level and to identify major computational and I/O bottlenecks. Refine the system model using multiple processors running various software tasks with communication among the processors.
3. Architecture | Microarchitecture Refinement – For each processor, profile the task performance and identify hot spots within each task. Configure each processor’s memories, add system peripherals, and select appropriate interprocessor interfaces. Use Tensilica’s tools to optimize each processor. Update power and area estimates. Use the automatically generated software tools and simulators. Refine the processor configurations until the overall design meets the per-task cost, power, and performance goals.
4. System Analysis and Early System Prototyping – Reintegrate each of the processor models (Tensilica automatically generates models that include all processor enhancements) and optimized tasks into the system-level model. Confirm that major partitioning and architectural choices are appropriate. Simulate the system using an instruction-set simulator to measure key performance characteristics. Check adequacy of shared resources (memory capacity, interconnect bandwidth, total silicon area, and power budget.) Deploy software-development tools and the system model to final application developers.
5. Detailed Implementation – Use the final RTL description for each processor, the generated memories, and other glue logic to floor plan, synthesize, place, and route each block. Stitch together global clocks, debug and test scan-chain hardware and the power infrastructure. Run full-chip logic, circuit, and physical design checks. Release to fabrication. Meanwhile, prepare for the final application and system software on the simulated or emulated system model. Perform initial system power-up testing and release the design to final system testing and production.

Making the SOC More Programmable

Using this new methodology, processors implement a much wider range of functions: both traditional software-based functions and traditional hardware-based functions. By using configurable, extensible processors as basic building blocks, design teams get greater programmability of all these functions and separating software tasks by running them on multiple processor cores reduces or eliminates the interference among tasks running on a single, larger, and more power-hungry processor.

Compared to hardwired function blocks, control from high-level-language applications running from RAM displaces finite-state-machine controllers implemented with logic gates. Because they deliver hardware-like performance, configurable processors increase performance headroom and allow incremental features to be incorporated without hitting a performance ceiling.

The processor-based SOC design approach helps get products to market much earlier and increases the likelihood that the design is correct as market requirements and standards evolve.

For more information, get a copy of the book “Engineering the Complex SOC: Fast, Flexible Design with Configurable Processors,” by Chris Rowen, published by Prentice Hall.