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METHODOLOGY

  Overview

  ESL Design

  C/C++ Design

  Speed RTL Design

  + Performace

  + I/O Throughput

  + No State Machines

  + GSM Codec Example

  + Viterbi Example

  + MPEG-4 Example

  + Low Power

  + Design Faster

  Multi Processor Dsgn

  Low Power Design

  Optimized with TIE

  EDA Design Flow

  System Modeling

Design Much Faster

Design Much Faster with a Processor

How do you get this blazing performance from an Xtensa processor? Xtensa processors can be quickly configured and extended to bring the required amount and type of processing bandwidth to bear on many embedded tasks, eliminating the time-consuming requirement to hard code algorithms in RTL.

You can use our XPRES Compiler to automatically examine your C/C++ algorithm and figure out the best possible configuration options and extensions for your design. Or you can decide what accelerators you want to add to the processors yourself.

Tensilica’s XPRES Compiler can take a quick (usually under one hour) look at your C/C++ algorithm and recommend several ways to extend the Xtensa processor to get the performance you need to run that algorithm without any RTL coding. The XPRES compiler uses a number of techniques (explained here) that allows it to get the 8X improvement shown in the EEMBC benchmark.

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SOC Book
RECOGNITION
Red Herring top 100
Read The Future of Multicore Processors from Instat/ Microprocessor Report
Read "More Patents for Tensilica" from In-Stat/Microprocessor Report
Portable Design 2006 Editor's Choice Award
EDN 100  Hot Products 2006
QUOTABLE

“We selected Tensilica’s Xtensa processor for its ability to help us achieve our goal of developing innovative-multi-gigabit, lower-power mmWave communications products. By optimizing the Xtensa processor into a tailored processor core, this enables our products to attain the performance these wireless applications demand.”

Kumar Mahesh, Manager of MAC and Software Design for SiBEAM, Inc.