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Tensilica’s Xtensa processors are widely
used in networking applications. Some examples of
networking applications include:
Xtensa processors are also ideal for applications
where throughput is critical and multiple data streams
must be quickly processed. One customer, Cisco Systems,
used 188 Xtensa processors in their design of the
world’s
largest router. Cisco’s Silicon
Packet Processor is optimized for scalability, availability, and the
ability to handle bandwidth at 40-gigabits of processing
per slot. That means a total capacity of 92 terabits
per second (Tbps), enough to transfer the entire
collection of the U.S. Library of Congress in fewer
than five seconds.
See the presentation given at the Linley Group Tech Seminar - CPU Cores and IP for Networking, January 31, 2007, Networking Applications for Xtensa Configurable Processors
Residential Gateway
As high-bandwidth access decreases in price for
residential Internet capabilities, subscription numbers
will go up and new applications such as on-demand
video will become more prevalent. At the same time,
connecting this high bandwidth throughout the residence
will require the gateway to perform many functions,
including modem, routing, WLAN, security, VoIP, etc.
Today, integrating these functions means combining
many different processor architectures into a single
chip, complicating the design task.
Tensilica’s Xtensa processor technology eases
the design of a system that requires multiple CPUs.
Tensilica’s
multiple processor simulation environment helps
system designers implement complex systems much more
rapidly than traditional design methods. Additionally,
custom instructions can speed up functions such as
VoIP, security, and packet inspection, allowing smaller,
more cost efficient designs. Tensilica’s
Xtensa configurable processors are extremely well
suited for low-cost, high-volume chips such as home
gateway controllers.
Xtensa Configuration Highlights
- Custom instructions for packet inspection
- Small control CPU cores for WLAN, modem, VoIP
- Main control processor runs platform OS (MMU)
Xtensa Benefits
- Support for multiple CPU cores in system design,
reduces time-to-market
- Custom instructions reduce silicon area; CPU
can eliminate dedicated hardware
- Fully programmable system can be kept current
while standards continue to evolve
TCP Offload Engine
High-performance enterprise networking equipment
must support tens of gigabits data rates while performing
tasks such as header examination, table lookup, packet
classification, QOS, etc. Existing network processors
based on standard CPU architectures are not flexible
enough to provide the bandwidth necessary to process
packets with increasing throughput requirements.
But programmable architectures are preferred due
to increasing functionality required as networks
are used for more than simple data transport; audio
and video streams are becoming commonplace.
Due to the repetitive nature of packet processing,
Tensilica’s Xtensa processors are an excellent
fit for this function. Multiple processors can be
programmed to process individual data streams. Additionally,
Xtensa processors are very area efficient; a minimal
configuration is only 20-25K gates. Additionally,
Tensilica provides support for multiple
processor designs through its XTMP simulation
environment. Basing a system on fully programmable,
configurable CPUs allows the inclusion of new networking
requirements without re-designing the chip.
Xtensa Configuration Highlights
- Multiple, minimally configured processors
- Custom instructions for packet manipulation
- Flexible local single-cycle memory
Xtensa Benefits
- Multiple processor simulation environment speeds
time to market
- Ports
and Queues allow inter-processor communication
- Instruction extensions increase performance while
minimizing increase in die area and costs
Voice Over IP (VoIP) Processor
VoIP applications have traditionally included a
control processor for system tasks such as I/O and
user interface and a DSP dedicated to running various
VoIP codecs. The architectures of these two programmable
cores are very dissimilar in nature, requiring two
different development environments and complicated
system integration modeling. As VoIP rises in popularity,
costs are becoming extremely important as end-user
equipment undergoes pricing pressure.
Tensilica’s Xtensa processor can combine the
standard control function of an embedded RISC controller
with the capability of being extended through custom
instructions to easily handle VoIP codecs. Not only
is system performance increased, resulting in lower
power consumption, but also a single architecture
can be utilized to perform both the control and data
processing functions. This results in lower system
costs and faster development time.
Xtensa Configuration Highlights
- Custom instructions for voice codec processing
- Lower gate count than most standard control
RISC control CPUs
- Multiple instructions issued per cycle
Xtensa Benefits
- Single development environment allows quicker
time to market
- Combining control CPU with DSP functions reduces
system costs
- VLIW
(FLIX) instruction encoding increases per
cycle performance
DSL Modem
DSL modems are outpacing cable modems in new subscriber
installations worldwide. As more on-line content
becomes available, ports shipped will increase dramatically.
A common system architecture for modems includes
both a control CPU and a separate DSP for data intensive
functions. As volume increases, pricing pressures
will force higher integration in DSL chipsets.
The DSL modem is an illustration of an application
that needs both a control CPU and a dedicated DSP
in the data plane. Tensilica’s Xtensa architecture
is well matched to this application, due to the ability
to run typical RISC control code while extending
the processor with instructions to enhance DSL signal
processing. This eliminates the need for a separate
DSP core, reducing system costs and development effort.
Xtensa Configuration Highlights
Xtensa Benefits
- Eliminate DSP core, reduces system costs
- Single programmable architecture for both control
and data
- Custom instructions provide performance levels
surpassing fixed DSP core
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