Line rates are on the rise, protocol standards are evolving, and you're being asked to add high-value Internet services such as VoIP, IPTV and video on demand. For intense communications and storage applications, you need fast, flexible processing engines that can be adapted to the exact datapath that needs to be efficiently processed. That's why companies like Cisco, Astute Networks, Bay Microsystems, Broadcom, Juniper Networks, NEC, NetEffect and Plato Networks picked Tensilica's DSPs and cores.
When it comes to the heavy lifting, Tensilica's Xtensa customizable processors can't be matched. Why hard code challenging algorithms in RTL when you can customize the datapath right inside an Xtensa processor? Here are the three biggest reasons companies pick Xtensa processors for servers, storage and communications infrastructure:
In networking it's all about speeds and feeds, but traditional processors are load/store bound. Xtensa augments data throughput via wider data busses and direct GPIO ports and FIFO queue interfaces - allow data to stream very quickly through multiple processors.
The more options, the better. You can configure Xtensa processors and pick from checklists of things you might, or might not, need. And it's easy to check to make sure you're making the right choices - Tensilica provides all the tools you need.
Traditional processors are limited to a fixed instruction set architecture (ISA). With Xtensa, you can invent new instruction to boost performance by 2x-100x or more. See examples of how our custom TIE instructions work. These custom instructions become native to Xtensa processors and are fully comprehended by the matching compiler and tool chain.
The fastest way to add custom instructions is to use Tensilica's XPRES Compiler, which analyzes your C-level software and recommends new instructions to boost performance. We recommend this as a first step, and we feel you'll be amazed at how this can really speed up your design effort.
Additionally, Tensilica's Diamond Standard and Xtensa processors are great embedded controllers for major subsystems in your designs.
Xtensa customizable processors are used extensively in layer 1, 2, 3 and 4 applications in PHYs, TOE engines, MACs, bridging and routing as well as packet classification and IPSEC (3DSE-CBC, AES-CBC). Xtensa processors have been used in applications with network speeds from DS-1 to 96 Gb/s.
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Cisco's CRS-1 Carrier Router System uses 192 Xtensa cores per SOC, allowing it to seamlessly scale up to 92 terabits per second. Cisco's Aggregation Services Router (ASR) 1000 Series router performs various edge networking functions at rates up to 20 Gbits/second. It features a 1.3 billion transistor QuantumFlow Processor that includes 40 Tensilica cores, each of which can handle up to four threads. |
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| Cisco's CRS-1 Carrier Router | |
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Cisco's ASR1000 Router
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Juniper Networks (previously known as NetScreen) uses two Xtensa processors in its NetScreen-ISG 1000 and 2000 security gateways. |
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| Juniper NetScreen-ISG 2000 | |
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NEC iStorage NV8210
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NEC iStorage NV8220
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The Astute Pericles Chip
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Bay Microsystems Montego Chip
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Broadcom's BCM1500 (CALISTO) uses five Xtensa cores for packet-based network systems that deliver voice/data services. The Xtensa processors are used as supervisory and control processor elements within the CALISTO architecture, and it was selected because it was easy to use, provided robust performance, occupied the smallest possible silicon area, and delivered superior code density to reduce code memory footprint.
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NetEffect's 10Gb iWARP Ethernet Channel Adapter (ECA) is the first adapter that fully implements the iWARP Ethernet standard, allowing data center managers to realize more than 10Gbps throughput using existing Ethernet hardware and software, while radically improving processor utilization for applications that use networking. Created by the RDMA Consortium and IETF, iWARP is a series of extensions to Ethernet that virtually eliminate the CPU bottlenecks and overhead associated with networking when all features are implemented. |
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Plato Networks licensed the Diamond Standard 108Mini processor core for a 10 Gigabit Ethernet physical layer transceiver (PHY) chip design. Plato Networks is developing low-power single-chip 10 Gbps physical layer ICs for low-cost copper cabling based on the newly approved IEEE 10GBASE-T standard (802.3an). Pirooz Hojabri, vice president of engineering, Plato Networks, said, "The Diamond Standard 108Mini was the perfect fit from a size, power, code density, and cost perspective." |
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