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Designed Into Network Infrastructure Products

Because they can be optimized for network processing, Tensilica's Xtensa processors have been designed into a wide variety of network infrastructure products, including:

See the presentation given at the Linley Group Tech Seminar - CPU Cores and IP for Networking, January 31, 2007, Networking Applications for Xtensa Configurable Processors

Cisco CRS-1 Carrier Router System

Cisco's CRS-1 uses 192 Xtensa cores per SOC. The Cisco CRS-1 is the industry's only carrier routing system that seamlessly scales up to 92 terabits per second, and enables service providers to deliver the most scalable, available and flexible converged packet infrastructure. The CRS-1 can transmit information four times more rapidly and can expand to 100 times more overall capacity than any router in the industry. At its highest capacity, and with the appropriate infrastructure, the CRS-1 system could run an 850 kilobit-per-second (Kbps) connection to every household in the United States, transfer the entire collection of the US. Library of congress in 4.6 seconds, or simultaneously connect three billion telephone calls. See press release, EE Times article and Cisco web site for more information.

Cisco CRS-1 Router

The Cisco CRS-1 Router Uses 188 Xtensa Processors Per Chip


Cisco's Quantum Flow Processor


Cisco's Aggregation Services Router (ASR) 1000 Series router transforms edge networking by performing various functions at rates up to 20 Gbits/second. These functions include firewall, IPSec, virtual private networking, deep-packet inspection and session border control. It features a 1.3 billion transistor QuantumFlow Processor that includes 40 Tensilica cores, each of which can handle up to four threads. Read more about this in the EETimes article.

Juniper GigaScreen-3

Juniper Networks (previously known as NetScreen) uses two Xtensa processors in its NetScreen-ISG 1000 and 2000 security gateways.

Juniper NetScreen-ISG 2000

The Juniper NetScreen-ISG 2000

These are high-performance integrated security gateways that deliver scalable network access for enterprise, carrier and data center networks.

Bay Microsystems' Montego

Bay Microsystems' Montego Internetworking processor is based on Xtensa. The Montego NPU (network processor unit) is the world's first single-chip 10G programmable internetworking processor, traffic manager, and segmentation and reassembly (SAR) engine, with 32Gbps of switching capacity. Montego empowers network systems OEMs with a comprehensive single-chip solution that addresses carrier class applications from Ethernet aggregation and IP/MPLS to SAN/WAN interworking with agile bandwidth management.

Bay Microsystems Montego architecture

NEC's W-CDMA Base Station

The PHE (packet handling engine) in NEC's W-CDMA base station uses two Xtensa cores. "We needed a processor core that could be optimized by NEC engineers to meet our performance targets, scaled in a multi-processor configuration for flexibility, flow a software-oriented development flow for optimization and flow any process technology or standard ASIC flow to reduce cost," said Mr. Toshiaki Ohno, Senior Manager, Engineering at the Network Control Engineering Department of NEC IP Networks Division. "We looked at fixed-architecture, general-purpose CPUs plus ASIC solutions and we found out that these old approaches just could not meet performance, cost, and power dissipation targets as well as an optimized, configurable processor in an SOC."

Both Xtensa cores use special NEC-defined instruction extensions to deliver optimal power and performance. "Since our development schedule was so tight, we met the performance requirements through the use of powerful TIE extensions to the Xtensa processor. We easily made our overall performance targets because the TIE instructions deliver in one clock cycle what otherwise would take dozens of individual RISC instructions. This was quickly and easily done using Xtensa core technology," added Mr. Toshiaki Ohno.

NEC's W-CDMA base station

NEC's W-CDMA base station uses two Xtensa processors.

Broadcom BCM1500 for VoIP

Broadcom's BCM1500 (CALISTO) uses five Xtensa cores for packet-based network systems that deliver voice/data services. CALISTO is derived from Broadcom's unique signal processing architecture, and was designed as a hybrid DSP/RISC chip with an adaptive instruction set that makes it possible to reconfigure the interconnect and the function of a series of basic building blocks on a cycle-by-cycle basis. The Xtensa processors are used as supervisory and control processor elements within the CALISTO architecture, and it was selected because it was easy to use, provided robust performance, occupied the smallest possible silicon area, and delivered superior code density to reduce code memory footprint.

Broadcom's CALISTO BCM1500 Re-configurable Processor

CALISTO Test and Reference Platform

Transwitch OMNI products and T3BwP chip

Xtensa processors are inside Transwitch's OMNI products and T3BwP chip. TranSwitch's ATM/IP OMNI VLSI devices are used in customer premises equipment such as hubs, routers, switches, concentrators, multiplexers and terminals, as well as in next-generation networks, data transport, Internet access and Internet backbone applications. The TXC-OMNI Switch Element (OSE) is a 12-port time-space switch element. Any of the 12 input ports can be switched to any of the 12 output ports. Each OSE has an aggregate bandwidth capacity of 30 Gbps, scalable to multi-terabit levels in a 5-stage network. The TXC-OMNI chip set is highly programmable for wire speed applications.

T3BwP (TXC-06826) is a RISC processor based device that supports the requirements of next-generation channelized DS3 access systems. T3BwP integrates an M13 multiplexer, 28 DS1 framers, and a 672-channel DS0 cross-connect with an embedded high-performance microprocessor to provide a complete channelized DS3 solution on a single chip. The embedded processor runs the device driver and allows communication to an external host via high-level API messages. The T3BwP can be configured to support a variety of modes of operation, which allows for design flexibility.

Transwitch's T3BwP Channelized DS3 Access Solution (TXC-06826)

Crimson Microsystems Ruby CM4800 MSPP-on-a-Chip

The Ruby MSPP-on-a-chip is a highly integrated SDH/SONET framer, 10G VT/TU pointer processor and 22.5G VT/TU non-blocking cross-connect. With full line and path monitoring and termination plus the ability to switch VT/TU paths, Ruby extends MSPP equipment out to the access edge by enabling disruptively low cost points in next generation access edge MSPP equipment.

“The Xtensa platform reduced our development time significantly, and provided flexibility down the line for further customization. This gives us immeasurable peace of mind, knowing that our technology will be highly competitive today, and our development effort can be leveraged as we proceed down our Microcommunications Processor roadmap,�? said Deepak Rana, CEO of Crimson Microsystems.

NetEffect's 10Gbps iWARP Ethernet Channel Adapters

NetEffect's 10Gb iWARP Ethernet Channel Adapter (ECA) is the first adapter that fully implements the iWARP Ethernet standard, allowing data center managers to realize more than 10Gbps throughput using existing Ethernet hardware and software, while radically improving processor utilization for applications that use networking. Created by the RDMA Consortium and IETF, iWARP is a series of extensions to Ethernet that virtually eliminate the CPU bottlenecks and overhead associated with networking when all features are implemented.

 NetEffect Chip