Tensilica’s Diamond and Xtensa processors are ideal control processors and can be used as-is or tailored to match your performance targets. Tensilica’s processors fit three main profiles as control processors:

1. Compact RISC Controller
2. Medium-performance RISC Controller
3. High-performance RISC CPU

Compact RISC Controller

The majority of high volume consumer oriented SOC applications usually operate with a system clock rate of less than 200Mhz CPU frequency. These SOCs employ a basic RISC CPU for system control functions, which operates at the system clock frequency. Key CPU requirements in these types of applications are minimal gate count, good code density, and low power consumption.

Diamond Standard Controllers

Tensilica's Diamond Standard 108Mini and 212GP processors are the lowest power, highest performance compact RISC controllers on the market. Although the Diamond 108Mini CPU is smaller in die area than other 32-bit CPUs, its performance is extremely high, 250Mhz in a .13-micron G-type process (worst-case).

The Diamond 212GP CPU is a high performance, versatile, fully synthesizable 32-bit RISC SOC controller core. Not only is the Diamond 212GP efficient area-wise and power-wise, its local memory architecture provides outstanding flexibility and performance. DSP hardware support on chip reduces the need to include a separate DSP in the system design.

Xtensa as a Compact Controller

Tensilica’s Xtensa base configuration – with no added custom instructions – is an ideal match for any application requiring an efficient RISC controller. The Xtensa base configuration is a modern RISC CPU architecture with clear advantages over competing embedded microprocessors.

Xtensa Configuration Highlights

• 150Mhz worst-case frequency in 130 nm
• 20K to 35K gates depending on configuration options – half the size of competitors
• Low power consumption – less than .1 mW/Mhz
• Fully synthesizable

Xtensa Benefits

• Fast TTM with drop-in 32-bit RISC CPU
• Lower total system costs due to smaller size and better code density than competitors
• Low power consumption
• Synthesizable core allows full system prototyping in FPGA
• Deterministic real-time operation through optional single-cycle local SRAM

Typical Application: Digital Still Camera Chip with Small, Energy-efficient RISC Controller

Medium Performance RISC Processor

Many SOC applications require more performance headroom than offered by small 32-bit RISC controllers - usually some data processing is occurring in conjunction with strict system control. For example, a medium performance 32-bit controller may be utilized in a consumer-targeted SOC due to required multimedia features and system throughput requirements. This application could be running basic signal processing tasks on the main system CPU while still performing functions such as user interface and system I/O control. Tensilica’s Diamond Standard processors are easy drop-in controllers for these applications. Tensilica's Xtensa processors are capable of supporting medium performance controller applications with simple configuration changes - no added custom instructions required.

Diamond Standard Processors

The Diamond 212GP is the best combination of performance, area, and code efficiency for any controller application requiring mid to high performance. DSP hardware support on chip reduces the need to include a separate DSP in the system design. DSP support in the Diamond 212GP consists of a single-cycle 16bitX16bit MAC unit adding four dedicated 32-bit registers and a 40-bit accumulator. Its local memory architecture provides outstanding flexibility and performance, and designers can take advantage of its lockable cache and attach any size single-cycle instruction or data SRAM up to 128Kbytes.

The Diamond 232L is like the Diamond 212GP and adds a full-featured Memory Management Unit (MMU) for the Linux operating system. Combining the MMU with a flexible interrupt architecture and high performance, the Diamond 232L can easily meet the needs of a complex system running numerous applications.

Xtensa as a Mid-Range Controller

Tensilica's Xtensa 6 processor can be configured to provide exactly the level of performance and functionality required for your mid-range controller requirements.

Xtensa Configuration Highlights

• 250-350Mhz worst-case frequency in 0.13 m m
• 32-bit hardware multiplier for basic DSP support
• Flexible cache and local memory options
• 80K-100K gates

Xtensa Benefits

• Hardware multiplier instruction options offer significant application speedup compared to basic RISC cores
• Large (up to 512Kbyte) local single-cycle memory configuration options. High-frequency operation still attainable due to designer-selectable 5-stage or 7-stage pipeline configuration option
• Lower total system costs due to smaller size, lower power consumption, and better code density than competitors

Typical Application: PDA Chip Running Platform OS

High-Performance RISC CPU

RISC system controllers are increasingly required to support data-intensive applications while still maintaining flexibility provided by software programmability. This has forced SOC CPU designers to push frequencies to well over 350Mhz in 130 nm processes. Due to the need to attain these frequencies in standard foundry processes, RISC CPU complexity has increased dramatically with to micro-architectural requirements such as long 8 or 9-stage pipelines, dynamic branch prediction, and separate ALU and load/store execution paths.

Tensilica's High-End Diamond Standard Processor

The Diamond 570T is among the highest performance, highest throughput licensable embedded CPUs available today. It combines an efficient 5-stage pipeline architecture with 3-issue VLIW instruction encoding, which enables it to obtain leading performance levels on both control code and DSP code, according to EEMBC benchmarks.

Tensilica's Xtensa LX Configurable Processor

Tensilica’s Xtensa LX processor easily surpasses the performance (on EEMBC benchmarks) of the most popular high-end controller cores from other IP vendors due to techniques that increase the amount of processing done per cycle. The Xtensa LX processor can be effortlessly configured to employ Very Long Instruction Word (VLIW), fused instructions, and Single Instruction, Multiple Data (SIMD) methods to raise performance levels beyond those of any other licensable CPU controller.

Xtensa Configuration Highlights

• Highest performance control CPU (on EEMBC benchmarks) vs. MIPS 20Kc and ARM10
• VLIW and SIMD techniques
• Flexible cache and local memory options
• 100-150K gates

Xtensa Benefits

• Performance leadership – headroom allows more tasks to be done in software
• Performance can be increased on applications 10X-100X using custom instructions
• Much smaller die size than competitors

Typical Application: Applications Processor