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Tensilica's Processors for Control

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The Ideal Deeply Embedded Control Processors

While they excel as complex dataplane processors (DPUs) and DSPs, many of our customers use our Diamond Standard and Xtensa processors for control, both as the main SOC controller and as the controller for deeply embedded dataplane blocks. Our cores can be used as-is or tailored to match your performance targets. Here are three typical use models:

Compact RISC Controller

The majority of high-volume consumer-oriented SOC applications usually operate at the lowest allowable clock frequency in order to conserve power. These SOCs employ a basic RISC CPU for system control functions, which operates at the system clock frequency. Key CPU requirements in these types of applications are minimal gate count, good code density, and low power consumption.

Diamond Standard Controllers

Tensilica's Diamond Standard 106Micro processor is among the lowest power, highest performance compact RISC controllers on the market. Although the Diamond 106Micro controller is smaller in die area than most other 32-bit CPUs, its performance will surprise you - there's no problem getting well over 500 MHz in 40 and 45 nm process technologies.

The Diamond Standard 106Micro is just the start of the upward-compatible Diamond Standard family, all of which are based on the Xtensa architecture. So if you like one of our Diamond Standard processors, but would like to customize it to fit your particular application, you can use Xtensa processors.

Xtensa as a Compact Controller

Tensilica’s Xtensa base core configuration – with no added custom instructions – is an efficient RISC controller. The Xtensa base configuration is a modern RISC architecture with clear advantages over competing embedded controllers.

Xtensa Configuration Highlights

20K to 35K gates depending on configuration options – half the size of competitors
Low power consumption – less than .1 mW/Mhz
Fully synthesizable

Xtensa Benefits

Fast TTM with drop-in 32-bit RISC architecture
Lower total system costs due to smaller size and better code density than alernative architectures
Low power consumption
Synthesizable core allows full system prototyping in FPGA
Deterministic real-time operation through optional single-cycle local SRAM

Typical Application: Digital Still Camera Chip with Small, Energy-efficient RISC Controller

Medium Performance RISC Processor

Many SOC applications require more performance headroom than offered by small 32-bit RISC controllers - usually some data processing is occurring in conjunction with strict system control. For example, a medium performance 32-bit controller may be utilized in a consumer-targeted SOC due to required multimedia features and system throughput requirements. This application could be running basic signal processing tasks on the main system CPU while still performing functions such as user interface and system I/O control. Tensilica’s Diamond Standard processors are easy drop-in controllers for these applications. Tensilica's Xtensa processors are capable of supporting medium performance controller applications with simple configuration changes - no added custom instructions required.

Diamond Standard Processors

The Diamond 212GP is the best combination of performance, area, and code efficiency for any controller application requiring mid to high performance. DSP hardware support on chip reduces the need to include a separate DSP in the system design. DSP support in the Diamond 212GP consists of a single-cycle 16bitX16bit MAC unit adding four dedicated 32-bit registers and a 40-bit accumulator. Its local memory architecture provides outstanding flexibility and performance, and designers can take advantage of its lockable cache and attach any size single-cycle instruction or data SRAM up to 128Kbytes.

The Diamond 233L is similar to the Diamond 212GP and adds a full-featured Memory Management Unit (MMU) for the Linux operating system. Combining the MMU with a flexible interrupt architecture and high performance, the Diamond 233L can easily meet the needs of a complex system running numerous applications.

Xtensa as a Mid-Range Controller

Tensilica's Xtensa DPU can be configured to provide exactly the level of performance and functionality required for your mid-range controller requirements.

Configuration Highlights

Very small, low power
32-bit hardware multiplier for basic DSP support
Flexible cache and local memory options

Benefits

Hardware multiplier instruction options offer significant application speedup compared to basic RISC cores

Large (up to 512Kbyte) local single-cycle memory configuration options. High-frequency operation still attainable due to designer-selectable 5-stage or 7-stage pipeline configuration option
Lower total system costs due to smaller size, lower power consumption, and better code density than alternative architectures

Typical Application: PDA Chip Running Platform OS

High-Performance RISC CPU

RISC system controllers are increasingly required to support data-intensive applications while still maintaining flexibility provided by software programmability. This has forced SOC CPU designers to push frequencies to well over 500 Mhz in submicron processes. Due to the need to attain these frequencies in standard foundry processes, RISC CPU complexity has increased dramatically with to micro-architectural requirements such as long 8 or 9-stage pipelines, dynamic branch prediction, and separate ALU and load/store execution paths.

Tensilica's High-End Diamond Standard Processor

The Diamond 570T is among the highest performance, highest throughput licensable embedded CPUs available today. It combines an efficient 5-stage pipeline architecture with 3-issue VLIW instruction encoding, which enables it to obtain leading performance levels on both control code and DSP code.

Tensilica's Xtensa LX Configurable DPU

Tensilica’s high-end Xtensa LX DPU easily surpasses the performance of the most popular high-end controller cores from other IP vendors due to techniques that increase the amount of processing done per cycle. The Xtensa LX processor can be effortlessly configured to employ Very Long Instruction Word (VLIW), fused instructions, and Single Instruction, Multiple Data (SIMD) methods to raise performance levels beyond those of any other licensable CPU controller.