Japan
Xtensaカスタマイザブル・プロセッサ
Product Briefs
Articles
Microprocessor Reports' December 2009 review of Xtensa LX3 and Xtensa 8
White Papers
The What, Why and How of Configurable Processors
How to Increase ASICs and SOC Computational Performance with Long-Word Processors
Processor Ports and Queues: Easily Overcome I/O Bandwidth Obstacles in Your Next ASIC or SOC Design
Videos
Processor Configuration with Chris Rowen
Bring Programmability to the Dataplane
Without sacrificing performance and bandwidth
Tensilica provides SOC designers with everything needed to quickly design small, low power and high-speed dataplane processors that exactly match the required application. By using Tensilica’s Xtensa dataplane processing units (DPUs), design teams can significantly reduce the development and verification time required by hand-coding RTL blocks in Verilog or VHDL. As these DPUs provide programability into the dataplane, changes can be made in firmware after silicon production that extend the life of the product as standards develop and market needs change.
All Xtensa customizable processors have two essential features:
- Configurability - designers are offered a menu of checkbox and drop-down menu options so they can pick just the features they need - including multiple pre-verified DSP engines
- Extensibility - designers can add their own instructions, registers, register files, and much more using the Tensilica Instruction Extension (TIE) methodology. The designer only has to specify the functional behavior of the new data path elements in the TIE language (Verilog-like) and then the RTL and whole tool chain is automatically generated.
Complete with Matching SW Tool Chain
All of the tools, including the compiler, debugger and ISS, are automatically updated to match the configuration options and any custom extensions. The matching tool set is generated by the Xtensa Processor Generator at the same time the new processor RTL is created.
Processor CoresXtensa LX4Tensilica’s top-of-the-line product, Xtensa LX4 takes the configurable, extensible processor to the next level with RTL-equivalent bandwidth and highly parallel computational performance through SIMD and VLIW operations. This highly flexible processor is ideal for DSP solutions from simple Voice processing to high performance next generation LTE Baseband. Xtensa 9Tensilica's Xtensa 9 provides designers with a configurable, extensible DPU that is ideally suited as a small, lower power dataplane controller. Its unique configuration options let it connect directly to RTL blocks when the system bus is too slow or already overloaded. Comparison
|
DSPsXtensa DSPs
You can make any Xtensa processor into the DSP of your dreams by customizing it for your application. ConnX DSPsSee our ConnX DSP section for a full list of our ready-made DSP options ranging from an efficient 2-MAC DSP core to the BBE64 for LTE Advanced communications. Multimedia SolutionsHiFi Audio DSPsTurnkey 24-bit audio for SOC designs, with multiple-codec support. VideoTurnkey video solutions for SOC designs, with multiple-codec support. Development ToolsXtensa Processor Developers ToolkitTensilica has created the most advanced and powerful yet easy-to-use tools for processor customization. Tensilica’s Processor Developer’s Toolkit contains all the tools necessary to create, analyze, and build extremely high performance application-specific processors. Xtensa SW Developers ToolkitIf you need to develop application code for an Xtensa processor, the Xtensa Software Developer’s Toolkit (SDK) provides a comprehensive collection of code generation and analysis tools that will speed the development process. FPGA PrototypingThe Xtensa processor generator produces optimized, fully-placed FPGA components for any Xilinx-based SOC prototyping or hardware emulation platform. |
||||||||||||||||||||||||||||||||||||||||||||||||||||
