Emulation Strategies
Tensilica's customers can deploy a variety of strategies for emulation of SOC designs employing Diamond Standard processors.
Some Diamond Standard designers use the RTL source code provided to support FPGA-based boards of their own design as part of a comprehensive SOC methodology.
Other Tensilica customers use commercial emulation systems in their SOC design process. EVE (Emulation and Verification Engineering) is Tensilica's recommended provider of high-capacity FPGA-based system emulators for SOC designs of up to 50-million gates. EVE's ZeBu product is targeted for use in the system-integration phase of the design cycle where multiple logic blocks and embedded software must be verified together. EVE and Tensilica have partnered to provide seamless integration of Tensilica debug tools into the EVE development software environment. See ZeBu-Diamond product brief.
Avnet LX60 and LX200 FPGA Board Support
Avnet’s Xilinx Virtex-4 LX200 Development Kit for high-speed hardware-based simulations of its Xtensa configurable and Diamond Standard processor families. Now software developers can choose between the cost-effective Avnet LX60 board and the high-capacity Avnet LX200 board to speed their software design, debug and program optimization processes.
Tensilica’s software developers’ toolkits (SDKs) – consisting of an IDE (the Xtensa Xplorer integrated design environment), code development toolchain and Tensilica’s instruction set simulator (ISS) – work seamlessly with either Avnet FPGA board. The software tools include libraries that enable software developers to use standard C library functions such as printf to print out to the host PC and read/write from the hard disk of the host PC.
Designers using Tensilica’s processors can take maximum advantage of an Avnet Virtex-4 Development Kit to gather extensive hardware-based profiling information. With hardware-based profiling, developers can get s an execution profile of the program, which allows the developer to quickly pinpoint execution hotspots. This profile can be viewed graphically within Tensilica’s Xtensa Xplorer IDE.
Using feedback compilation, a developer can set a flag so the compiler instruments the compiled code to collect statistics on the number of times branches (loops, jumps, etc.) are taken or not taken during execution on the Avnet Xilinx Development Kit board. The Xtensa C/C++ compiler then uses these run-time generated statistics and recompiles the program to optimize (a) for speed by placing most frequently taken branches in straight-line code, and (b) for code size by compiling less frequently executed routines for code size rather than speed. The feedback-based compilation method speeds up applications between 5 to 15 percent and reduces code size by up to 15 percent.
Additionally, the Ethernet interface on the boards make them ideal for running an operating system such as Linux and the associated TCP/IP stack and network file systems.
Tensilica supplies users with precompiled FPGA bitstreams that support the LX60 and LX200 boards. Tensilica customers can use these bitstreams on an unlimited number of Avnet LX60 or Avnet LX200 boards, thus enabling development teams with large numbers of software designers to cost-effectively deploy a large number of development systems.
The two Avnet Xilinx Virtex-4 Development Kits are available directly from Avnet at:
The Avnet LX6 or LX2000 FPGA boards can be used with Diamond Standard 106Micro, 108Mini, 212GP, 232L, and 570T. The support package for the Diamond Standard 570T does not include Ethernet support.
The Avnet LX60 Board is Ideal for High-Speed Hardware-Based Simulations of Diamond Standard Processors
Emulation Flow for Diamond Cores
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This application note explains how to map an Xtensa or Diamond core to an FPGA with a minimal on-chip system. This application note includes a demonstration example of an FPGA flow based upon Xilinx logic using RTL for the 108Mini Diamond core.
Check out our Diamond FREE software evaluation.
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