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Diamond Standard Processors -
Comparison Matrixes

See Microprocessor Report's Write-up on Diamond Processors

Tensilica's Diamond Standard processor family covers the broadest range of performance of any embedded computing architecture. Here are several charts to help you figure out which processor core is best for your needs.

Diamond Standard Controllers - From Cache-less Controller to High-Performance VLIW CPU

Diamond Standard Controllers/CPU Selector Guide
Characteristic
106Micro
108Mini
212GP
232L
570T
Max Frequency
(90nm G)
400 MHz
400 MHz
400 MHz
350 MHz
400 MHz
Dhrystone MIPS/MHz 1.22
1.34
1.38
1.38
1.59
Area, post-synthesis (90nm G) 0.13 mm2
0.24 mm2
0.32 mm2
0.40 mm2
0.46 mm2
Area, post layout
(90 nm G)
0.145 mm2 (85%)
0.26 mm2 (85%)
0.36 mm2 (85%)
0.44 mm2 (85%)
0.52 mm2 (65%)
Power, mW per MHz (90nm G, typical conditions) 0.044
0.062
0.089
0.096
0.124
# Pipeline Stages 5
5
5
5
5
Instruction Width 16/24 bit 16/24 bit 16/24 bit 16/24 bit 16/24/64 bit 3-issue
General Purpose I/O Ports No Yes Yes Yes Yes
High-Throughput Data Queues (FIFOs) No No No No Yes

 

Hardware Features
  106Micro 108Mini 212GP 232L
570T
330HiFi 545CK
Pipeline stages 5 5 5 5 5 5 5
Instruction width (bits) 16/24 16/24 16/24 16/24` 16/24/64 16/24/64 16/24/64
Multiple instruction issue (static superscalar) no no no no 3 issue or 2 issue 2 issue 3 issue
Local memory data path width (bits) 32 32 32 32 64 64 64
General purpose registers 32 32 32 32 32 32 64
Custom vector registers N/A N/A N/A N/A N/A 8x48-bit & 4x56-bit 16x160-bit
Instruction cache size

N/A

N/A 8 Kbyte 16 Kbyte 16 Kbyte 4 Kbyte N/A
I-Cache associativity

N/A

N/A 2-way 4-way 2-way 2-way N/A
Data cache size N/A N/A 8 Kbyte 16 Kbyte 16 Kbyte 8 Kbyte N/A
D-Cache associativity N/A N/A 2-way 4-way 2-way 2-way N/A
Load/Store units 1 1 1 1 1 1 2
Local instruction RAM, user selectable size, maximum size 128 Kbyte 128 Kbyte 128 Kbyte N/A 128 Kbyte 128 Kbyte 128 Kbyte
Local data RAM, user selectable size, maximum size 128 Kbyte 128 Kbyte (dual) 128 Kbyte N/A 128 Kbyte 128 Kbyte (dual) 128 Kbyte (dual)
XLMI Interface no no yes no yes no no
Input/output ports (32 bits wide) no yes yes yes yes yes no
Input/output queues (32 bits wide) no no no no yes yes yes
System interface (PIF) width 32 32 32 32 64 64 128
MUL 16 yes yes yes yes yes yes yes
MAC 16-bit single cycle no no yes yes yes no no
32x32 MUL32 yes yes yes yes dual yes no
32-bit integer divide no yes yes yes yes no no
Sign Extend, NSA, MIN/MAX yes yes yes yes yes yes yes
Zero-overhead looping no no yes yes yes yes yes
Specialized DSP instructions no no no no no yes (audio) yes
External interrupts 12 16 16 16 16 16 16
Timer interrupts 1 3 3 3 3 3 3
Software interrupts 1 2 2 2 2 2 2
Non-maskable interrupt yes yes yes yes yes yes yes
On-chip debug (OCD) yes yes yes yes yes yes yes

Check out our Diamond FREE software evaluation.

FEATURED INFORMATION
See "Diamond Standard Software Tool Chain" on Demos on Demand
Portable Design 2006 Editor's Choice Award
PRODUCT RESOURCES
"Tensilica's Preconfigured Cores" by Microprocessor Report
Diamond Standard Series Product Brief
Diamond Tools Product Brief
HiFi 2 Audio Engine Product Brief
Diamond VDO Product Brief
Tensilica's Diamond Standard Processor Cores - CoolBeans Write-up
Diamond Free SW Eval
WHITE PAPERS
Diamond Architecture White Paper
PRESENTATIONS
Low Cost and Low Risk 32-bit Controllers for Designing AMBA-based SOCs
QUOTABLE

“Offering the option of preconfigured cores simply makes sense...The Xtensa architecture is so flexible, and the configuration tools so versatile, that Tensilica could generate hundreds, or even thousands, of preconfigured cores to meet almost every conceivable need."

Tom Halfhill,
Microprocessor Report