Tensilica's PIF
Tensilica’s PIF is an advanced, high-performance system bus which is the primary interface for all Tensilica processors, including the Xtensa and the Diamond Standard products. All external memories and peripheral devices are serviced by the PIF in a typical Tensilica processor-based system; additionally, the PIF is capable of receiving inbound requests from an external master such as a DMA. Sophisticated system bus features such as split-transactions and multiple outstanding requests are also defined by the PIF protocol.
For designers requiring the fastest time-to-market or using off-the-shelf SOC peripheral components, Tensilica offers two bridges:
The AHB-Lite Bridge
Features
- Converts all signals between Tensilica's PIF (Processor InterFace) and AMBA AHB-Lite (Advanced Microcontroller Bus Architecture 2.0, Advanced High-performance Bus)
- Widths of 32, 64 or 128 bits (PIF data width = AHB-Lite data width), matched to particular Diamond Standard processor
- Master and Slave capability
- Bus clocks can run at an integer fraction of the CPU clock (1:1, 1:2, 1:3, 1:4)
- Access to local memory through slave port does not stall processor
Benefits
- Quick time-to-market when integrating a Tensilica core into a legacy AHB-Lite-based system
- Variable data width optimizes performance vs. system complexity
- Slave capability allows external DMA into local single-cycle RAM
- CPU can run at maximum frequency by stepping down system bus frequency
- DMA to processor does not affect interrupt latency
Tensilica’s PIF to AHB-Lite bridge converts all signals between the AMBA and PIF protocols, which enables very simple hardware integration of a Tensilica processor into an AMBA 2.0 based system. Since AHB-Lite is a single-master protocol, multi-master systems are composed of multiple single-master subsystems referred to as “multi-layer AHB-Lite” systems. Multi-layer AHB-Lite systems are preferred over previous shared master systems because they can have higher performance (less congestion) and frequencies (less complexity). Since PIF also allows inbound capability, the bus bridge can function as an AHB master only or optionally an AHB master and slave in a multi-layer system.
All Diamond Standard Series processors include pre-configured Verilog for the bridge matched to the particular Diamond bus width, PIF signaling, and inbound PIF capability. Tensilica’s PIF to AHB-Lite bus bridge is the quickest, most flexible way to integrate Tensilica processors into any AMBA-based SOC design.
Quick hardware integration in a multi-layer AHB-Lite system is realized by the PIF to AHB-Lite Bridge, which allows both AMBA AHB Master and Slave capability.
All signals between PIF and AMBA 2.0 AHB-Lite are converted by the Bridge, minimizing CPU hardware integration time
The AXI Bridge
Features
- Converts all signals between Tensilica's PIF (Processor InterFace) and AMBA AXI
- Widths of 32 or 64 bit (PIF data width = AXI data width), matched to particular Diamond Standard processor.
- Simultaneous read and write transactions
Benefits
- Quick time-to-market when integrating a Tensilica core into a legacy AXI-based system
- Pipelined interconnect for high-speed operation
Tensilica’s PIF to AXI bridge converts all signals between the AMBA and PIF protocols, which enables very simple hardware integration of a Tensilica processor into an AMBA 3.0-based system.
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