A Universal Architecture for All Markets
Tensilica’s Diamond Standard processors are based on Tensilica's proven Xtensa architecture, which is used across a wide range of electronic products, from low-cost portable consumer applications to carrier-class networking routers. Whether used as an efficient programmable controller or as an audio processor, high-performance DSP or high-speed processor, the Xtensa Instruction Set Architecture (ISA)-based Diamond Standard Series is the ideal architecture for almost any application in any market. The combination of small die area, high performance, and low power consumption place the Diamond Standard Series beyond all other competing 32-bit RISC architectures.
See our Diamond Standard Series Architecture White Paper.
The Xtensa architecture is proven in many applications including:
The Diamond Standard Series implements the Xtensa Instruction Set Architecture (ISA), a 32-bit RISC architecture featuring a compact instruction set optimized for embedded designs. The architecture has: a 32-bit ALU; 16, 32 or 64 general-purpose physical registers; six special purpose registers; and 80 base instructions. The Xtensa ISA employs 24-bit instructions with 16-bit narrow encodings for the most common instructions. These 16-and 24-bit instruction words are freely intermixed to achieve higher code density without compromising application performance. On some processors, 64-bit VLIW encoding is utilized when efficient, and these 2- or 3-issue instructions are also modelessly intermixed with 16- and 24-bit instructions. The Xtensa ISA thus optimizes the size of the program instructions by minimizing both the static number of instructions (the instructions that constitute the application program) and the average number of bits per instruction.
The use of 24- and 16-bit instruction words, the use of compound instructions, the richness of the comparison and bit-testing instructions, zero-overhead-loop instructions, register windowing, and the use of encoded immediate values all contribute to the Diamond processors’ small code size. Thus, the 24-/16-bit Diamond processor ISA enables designers to achieve 25% to 50% lower code size compared to conventional 32-/16-bit ISA-based RISC cores. Reducing code size results in smaller memory sizes and lower power dissipation – key parameters in cost-sensitive, highly integrated SOC designs.
Tensilica's Xtensa architecture is much more efficient and results in smaller code size than ARM and MIPS.
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The Xtensa ISA also provides powerful compare-and-branch instructions, zero-overhead loops, and bit manipulations including funnel shifts and field-extract operations.
For more information on the Xtensa ISA, download the PDF of the ISA databook.
Ideal for Applications Where Low Power is Critical
Clock gating is a very effective power reduction technique that reduces power by stopping unnecessary clocking activity to parts of the logic that are not in use on a particular clock cycle. Tensilica has designed fine-grained clock gating for every functional element of these processors into the Diamond Standard Series. The Diamond Standard Series processor architecture dramatically lowers power consumption since it is designed to use power very efficiently. As an example, the Diamond 108Mini processor dissipates less than 60 µW/MHz in a representative 0.13 µm process technology.
Extremely High-Speed I/O with Ports and Queues
Most Diamond Standard processor cores utilize Tensilica’s proven Ports and Queues capabilities for extremely high-speed input/output, bypassing the system bus. Ports allow designers to construct I/O registers completely separate from the main system bus and directly accessible from any peripheral in the system. I/O ports are included in the 108Mini, 212GP, and 570T cores. Queues take this idea further; allowing FIFO flow controlled I/Os completely accessible from the base CPU and external logic blocks. Queues enable ultra-high, dedicated data bandwidth processor-to-processor or processor-to-RTL and eliminate main system bus data contention, one of the most common problems in complex system-level silicon design today. 32-bit input/output queues are included in the 570T, 545CK and 330HiFi.
Eliminate External Interrupt Controller
All Diamond Standard processors include a rich interrupt architecture that, in most cases, eliminates the need for a separate controller. Nine external interrupts at different hardware-defined priority levels provide system flexibility; additionally, three timer interrupts and two software interrupts are available. For extreme time-critical applications, a non-maskable interrupt is included. The Diamond Standard interrupt architecture is among the most flexible for any CPU or DSP.
Optional AMBA Bridges
Tensilica provides an optional bridge from Tensilica’s Peripheral Interface (PIF) bus to a system based on AMBA AHB lite (single master) or AXI. Hardware developers who are familiar with the AMBA busses can quickly integrate the Diamond cores into their systems. This is especially beneficial to system designers who are modifying an existing hardware platform and are replacing their control CPU, allowing quick design and time-to-market. For designers utilizing an alternate system bus, the PIF interface can be easily bridged to the system bus of choice.
Diamond Standard Series Features
Processor Architecture
- High-performance 32-bit RISC with 5-stage pipeline
Instruction Set
- Xtensa ISA with compact 16-bit and 24-bit base instruction set
- VLIW-enabled processors add 64-bit instructions*
Execution Unit and ISA
- Multipliers: 32- and/or 16-bit*
- Integer divider*
- Single 16-bit MAC*
Bus Interface
- Processor interface (PIF)
– Width: 32/64/128-bit*
– Inbound DMA access for local data RAM
- XLMI high-speed local interface*
- Little-Endian or Big Endian byte ordering*
- On-chip debug port
- 15 interrupts (external and internal) including non-maskable interrupt
- Optional RTL for AMBA AHB Lite <-> PIF bus bridge (symmetric data bus widths, 32-, 64-, or 128-bit) or the AMBA AXI bridge
- Ports and Queues – Direct CPU <-> system peripheral data busses, bypassing main system bus*
Memory Subsystem
- Memory Management
– Region Protection*
– Memory Management Unit (MMU) with Translation Look Aside Buffers (TLBs)*
- Local data and instruction caches*
– 2-way or 4-way set associative
– Programmable write-back and write-through cache policies
- Separate local RAM areas for data, instructions, user selectable sizes up to 128Kbytes*
- Two data RAM interfaces enable simultaneous CPU and external DMA operation*
Design Support
* Not included in all cores, see specific core descriptions
Check out our Diamond FREE software evaluation.
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