Contents

• Features
• Benefits
• Description
• Frequency, area and power specs
• Block diagram
• Instruction formats
• Competition

Features

• Ultra-high-performance RISC CPU core
• Two- or three-issue, static-superscalar Very Long Instruction Word (VLIW)
• Modeless switching between 16-, 24- and 64-bit instructions
• Compiler automatically creates VLIW instructions
• Dhrystone 2.1: 1.59 DMIPS/MHz
• Dual 32x32 SIMD MULs and 32-bit integer divider
• 16-bit DSP instructions
• 16 Kbyte, 2-way set associative I & D caches, programmable write-through or write-back
• Single-cycle I & D SRAM interface
• High-speed peripheral port (XLMI)
• Memory protection unit
• 64-bit PIF interface
• On-chip debugging hardware
• Embedded trace support
• 32-bit GPIO and FIFO interfaces
• AHB-lite and AXI bridges

Benefits

• Highest performance CPU per EEMBC benchmarks
• Compiler maps C/C++ automatically to boost performance; simple programming model
• High arithmetic and DSP performance, eliminating need for separate DSP
• Fast and flexible interrupt handling
• Bypass system bus and communicate directly via GPIO and FIFO interfaces
• Drop into existing AMBA-based SOCs

Static-Superscalar Controller Core

The Diamond Standard 570T is among the highest performance, highest throughput licensable CPUs available today. It combines an efficient 5-stage pipeline with a 3-issue VLIW architecture, which enables it to obtain leading performance levels on both control code and DSP code, when benchmarked using EEMBC benchmarks.

Due to the Diamond 570T’s flexible base architecture, 16-, 24-, and compound 64-bit VLIW instruction bundles can be freely intermixed in the instruction stream with no processor mode switching, thus maintaining performance while optimizing code size. The compiler automatically creates 64-bit VLIW instruction bundles if instructions can be issued simultaneously; otherwise, a single 16/24-bit instruction is issued. This capability increases code density to industry leading levels, reducing the amount of on-chip cache or memory required for storage of instructions.

The Diamond 570T includes many standard DSP instructions to increase performance of numerically intensive applications, plus a 32x32 multiplier and 32-bit integer divider. Example DSP instructions include: zero-overhead looping, clamps (saturating arithmetic), max/min value, normalize, and sign extend. Additionally, a MAC unit enables high performance on inner loops requiring fast multiplication.

The Diamond 570T also includes 32-bit input/output GPIO ports and 32-bit input/output FIFO interfaces, which can be used to connect to standard FIFOs for fast communication with other RTL blocks, devices, and processors without ever using the system bus for maximum throughput.

Get the 2-page Diamond Standard 570T product brief.

Frequency, Area and Power Specs

130G and 90G are with TSMC Sage-X libraries.
Area and frequency at worst operating condition (0.9 * Vdd, 132 C)
Power at typical operating condition (1.0 * Vdd, 25 C)
All area, power, and frequency numbers are representative only, and subject to variation based on each user's chosen process technology, cell library, and design tools. See white paper: Processor Core Power Specs: A Cautionary Tale

Block Diagram of the Diamond Standard Series 570T

Check out our Diamond FREE software evaluation.

Diamond 570T Instruction Formats

The Diamond 570T uses 16-, 24- and 64-bit instructions. By wisely only using large instructions when needed, the Diamond 570T provides code-efficient VLIW-like performance. Four instruction formats are supported, as shown below.

The compiler automatically modelessly intermixes these different instruction formats for maximum efficiency.