Contents
Features
- Highest performance and efficiency of any licensable DSP core
- 3-issue VLIW DSP with 8-way SIMD units
- Compiler automatically vectorizes code
- DSP instructions native to single core, modeless switching between 16-, 24- and 64-bit instructions
- Dual 128-bit load/stores
- Eight 16-bit multipliers that operate in SIMD mode
- 16-entry, 160-bit-wide vector register file
- Two 128-bit load/store units
- 32-bit input/output FIFO interfaces
- Viterbi convolutional coder accelerator
- AHB-lite and AXI bridges
Benefits
- Very high and flexible computational performance
- Performance headroom allows operation at lower frequency to reduce power consumption
- Single core, single development environment due to native DSP instructions
- Ideal for communication baseband applications
- Very high I/O throughput; higher than XY DSPs
- Bypass system bus and communicate directly via FIFO interfaces
- Drop into existing AMBA™-based systems
Highest Performance DSP Core
The Diamond Standard 545CK is the highest performance licensable DSP IP core. The Diamond 545CK, which combines a base CPU controllers and a DSP containing eight parallel 16-bit single-cycle MAC units, allows system control and industry leading data processing throughput in a single core with a single compiler and single instruction stream. The Diamond 545CK can sustain eight simultaneous MAC operations on independent data pairs per cycle, utilizing the 160-bit vector registers.
As in all Xtensa ISA-based architectures, 16-, 24- and 64-bit VLIW instruction bundles can be freely intermixed in the instruction stream with no processor mode switching to decrease performance. All software development tools (compiler, linker, debugger, instruction set simulator) have been enhanced to enable access to DSP-related and control hardware through standard C/C++ source code.
In addition to the data processing gains realized through parallel multiplier hardware, the Diamond 545CK includes support for other DSP-related operations, such as zero-overhead looping, clamps (saturating arithmetic), max/min value, normalize, and sign extend.
The Diamond 545CK is an industry leading combination of an efficient 32-bit RISC controller and an extremely high-performance DSP in a single licensable IP core. It eliminates the need to develop SOCs with separate control and DSPs.
Get the 2-page Diamond Standard 545CK product brief.
Frequency, Area and Power Specs
Area (mm2) post-synthesis |
2.48 |
2.22 |
1.29 |
1.09 |
Cell a rea (mm2) post-layout |
3.58 |
2.88 |
1.76 |
1.34 |
Freq (MHz) post-layout |
233 |
125 |
350 |
200 |
Power (mW/MHz) post-layout |
0.464 |
0.412 |
0.199 |
0.163 |
For new 65LP numbers, please contact your local Tensilica salesperson for more detailed information.
130G and 90G are with TSMC Sage-X libraries.
65GP is with TSMC Advantage library, Regular Vt.
65LP is with TSMC library (Synopsys), Regular Vt.
Area and frequency at worst operating condition (0.9 * Vdd, 132 C)
Power at typical operating condition (1.0 * Vdd, 25 C)
All area, power, and frequency numbers are representative only, and subject to variation based on each user's chosen process technology, cell library, and design tools.
See white paper: Processor Core Power Specs: A Cautionary Tale
*Area is post synthesis, post layout, assuming 50% utilization.
Performance Comparison
Diamond 545CK is faster than every other licensable DSP core or CPU core tested by BDTI
All scores use worst-case clock speeds for the TSMC CL013G process and ARM Artisan SAGE-X library.
The BDTIsimMark2000™ is a summary measure of DSP speed. See www.BDTI.com for info. Scores © 2007 BDTI.
Low Power
In addition, the Diamond 545CK achieves a BDTIsimMark2000TM per-mW score of 80. This is over 2x more energy efficient than any other core benchmarked by BDTI to date (as of February 2006).
Block Diagram of the Diamond Standard Series 545CK
Check out our Diamond FREE software evaluation.
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