Contents:

• Features
• Benefits
• Description
• Frequency, area and power specs
• Block diagram
• Competition

Features

• Ultra-low power, small area RISC controller
• Cache-less processor with memory protection unit
• 5-stage pipeline
• Dhrystone 2.1: 1.34 DMIPS/MHz
• 24/16-bit ISA with modeless switching
• 32x32 multiplier and 32-bit integer divider
• Separate instruction and data memory interfaces
• Dual local data RAMS
• 32-bit input/output GPIO pins for direct communication
• Integrated interrupt controller with 22 interrupts at 6 priority levels
• Three integrated timers
• On-chip debugging hardware
• Comprehensive software design environment
• AHB-lite and AXI bridges

Benefits

• Lower total die area due to smaller core area and better code density
• Deterministic real-time operation through single cycle local instruction and data SRAMs
• Achieve high frequency: 400 MHz in 90G
• High arithmetic and DSP performance
• No memory contention between instructions and data
• Dual data RAMS allow ping-pong – read/write one, DMA into other
• Fast and flexible interrupt handling
• Drop into existing AMBA-based SOCs

Minimal Gate Count for Low Silicon Cost

The Diamond Standard 108Mini CPU is a fully synthesizable 32-bit RISC CPU controller core. It is a small, cache-less RISC controller with tightly-coupled local instruction and data memories, a rich interrupt architecture, and high arithmetic and DSP performance. It enables SOC architects to integrate an efficient CPU in their designs, with the added benefit of extremely quick time-to-market. The Diamond 108Mini features class-leading low-power consumption for portable applications.

Although the Diamond 108Mini is smaller in die area than comparable 32-bit CPUs, its performance is extremely high: 420 MHz in a 90nm G process and achieving 1.34 Dhrystone MIPS/MHz. It also achieves high performance on DSP applications and engine and motor control applications because of the built-in 32x32 multiplier and 32-bit integer divider.

The Diamond 108Mini delivers fast and flexible interrupt handling with the availability of low interrupt latency and a rich interrupt architecture. The processor has deterministic behavior for applications with hard real-time constraints. 32 base registers are windowed 16 at a time, which enables much faster context switching due to reduced stack operations. Local single-cycle SRAM allows time critical code to be placed near the CPU. Dual local data SRAM enables processor access to one bank of RAM while an external DNA operation can operate on the other bank. Separate instruction and data memory interfaces lead to lower contention than unified interface architectures.

While small and low power, the Diamond 108Mini achieves the performance levels of much larger, complex CPUs.

Get the 2-page Diamond Standard 108Mini product brief.

Frequency, Area and Power Specs

130G and 90G are with TSMC Sage-X libraries.
65GP is with TSMC Advantage library, Regular Vt.
Area and frequency at worst operating condition (0.9 * Vdd, 132 C)
Power at typical operating condition (1.0 * Vdd, 25 C)
All area, power, and frequency numbers are representative only, and subject to variation based on each user's chosen process technology, cell library, and design tools. See white paper: Processor Core Power Specs: A Cautionary Tale

Block Diagram of the Diamond Standard Series 108Mini

Check out our Diamond FREE software evaluation.