A Full 32-bit Core Available for Free* Through Synplicity's Synplify Pro and Synplify Premier Software
| The Diamond Standard 106Micro CPU, based on the industry-standard Tensilica Xtensa architecture, is ideal for designers looking for a basic 32-bit controller, particularly for those migrating up from an 8- or 16-bit controller. The Diamond 106Micro can be used with any FPGA device, including those from Xilinx, Altera, Atmel and Lattice, and is available only through Synplicity’s Synplify Pro and Synplify Premier software. |
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* The click-through license explains the terms of use for FPGA designers. With no up-front licensing fee and no royalties until 10,000 units, the Diamond Standard 106Micro is essentially free for many FPGA designers.
A Full-Featured 32-bit Controller Core
Although the Diamond 106Micro is extremely small, it employs a 5-stage pipeline, whereas many 32-bit cores for FPGAs only employ 3-stage pipelines. By modelessly switching between 24- and 16-bit narrow instructions, it achieves a much higher code density than other 32/16-bit architectures.
The local, tightly-coupled instruction and data memory on the Diamond Standard 106Micro can be used to store performance-sensitive code and data, for example, to achieve high performance on interrupt handlers.
The Diamond 106Micro has an iterative, multi-cycle 32x32 multiplier that greatly enhances performance on arithmetic and DSP code.
The Diamond Standard 106Micro has a rich interrupt architecture with an integrated interrupt controller with 15 interrupts, and an integrated timer. This simplifies system design since no external hardware needs to be added for these functions.
The Diamond 106Micro also includes an integrated timer and on-chip debug.
Comprehensive Software Tool Support
A full-featured development environment – the Xtensa® Xplorer™, Diamond Edition – provides a graphical user interface (GUI) to all code development tools. The compiler toolchain and instruction set simulator (ISS) are available through the GUI in addition to performance modeling tools. Based on the Eclipse framework, Xtensa Xplorer allows developers to quickly evaluate code on the pipeline-accurate ISS and interface to emulation and hardware development boards. Xtensa Xplorer serves as the cockpit for the entire development experience and integrates the compiler tool chain as well as the ISS and interfaces to hardware emulation/development boards.
Tensilica's XCC C/C++ compiler is an optimizing compiler that employs sophisticated multi-level optimizations to increase code execution performance and reduce code size .
Also included in the Xtensa Xplorer environment are a software project manager, code profiling tools, a source code editor, a debugger, a performance-modeling tool, the Xenergy energy estimation tool, a cache performance explorer, and graphical visualization tools. Tensilica also provides both a C-based modeling environment called XTMP and SystemC models of the Diamond processors.
For More Information
See the Diamond Standard 106Micro product brief.
See the Diamond Software product brief.
Contact Synplicity for more details.
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