Now Available for FPGAs

Contents:

• Features
• Benefits
• Description
• Frequency, area and power specs
• Block diagram
• Competition

Features

• Smallest, lowest power 32-bit RISC controller core
• Cache-less processor with memory protection unit
• 5-stage pipeline
• Dhryston MIPS: 1.22 DMIPS/MHz
• 24-/16-bit ISA with modeless switching
• Iterative 32x32 multiplier
• Separate instruction and data memory interfaces
• Integrated interrupt controller with 15 interrupts at 2 priority levels
• Integrated timer
• On-chip debugging hardware
• Embedded trace support
• Comprehensive software design environment
• AHB-lite and AXI bridges

Benefits

• Easy migration from 8- and 16-bit microcontrollers
• Lower total system costs due to smaller size, higher performance, and better code density
• Deterministic real-time operation through optional single-cycle local instruction and data SRAMs
• Achieve high frequency: 400 MHz in 90G
• Multiplier provides high arithmetic and DSP performance
• No memory contention between instructions and data
• Fast and flexible interrupt handling
• Drop into existing AMBA™-based SOCs

The Smallest 32-bit RISC Controller Core

The Diamond Standard 106Micro CPU is the smallest 32-bit RISC controller based on an industry-standard architecture, designed for lowest area and lowest power. This cache-less controller is ideal for designers looking for a basic 32-bit controller, particularly for those migrating up from an 8- or 16-bit controller. It enables SOC architects to integrate an efficient CPU in their designs, with the added benefit of extremely quick time-to-market.

Although the Diamond 106Micro is extremely small, it employs a 5-stage pipeline so it can easily achieve 400 MHz in 90G process and up to 610 MHz in 65G process technology. By modelessly switching between 24- and 16-bit narrow instructions, it achieves a much higher code density than other 32/16-bit architectures.

The local, tightly-coupled instruction and data memory on the Diamond Standard 106Micro can be used to store performance-sensitive code and data, for example, to achieve high performance on interrupt handlers.

The Diamond 106Micro has an iterative, multi-cycle (non-pipelined) 32x32 multiplier that greatly enhances performance on arithmetic and DSP code. The processor uses a non-windowed 16-entry AR register file to keep area low and that potentially does better on applications that have very deeply nested function calls, since it never throws an exception.

The Diamond Standard 106Micro has a rich interrupt architecture with an integrated interrupt controller with 15 interrupts, and an integrated timer. This simplifies system design since no external hardware needs to be added for these functions.

Get the 2-page Diamond Standard 106Micro product brief.

Frequency, Area and Power Specs

For new 65LP numbers, please contact your local Tensilica salesperson for more detailed information.

130G and 90G are with TSMC Sage-X libraries.
65GP is with TSMC Advantage library, Regular Vt.
65LP is with TSMC library (Synopsys), Regular Vt.
Area and frequency at worst operating condition (0.9 * Vdd, 132 C)
Power at typical operating condition (1.0 * Vdd, 25 C)
All area, power, and frequency numbers are representative only, and subject to variation based on each user's chosen process technology, cell library, and design tools. See white paper: Processor Core Power Specs: A Cautionary Tale

Block Diagram of the Diamond Standard Series 106Micro

Check out our Diamond FREE software evaluation.