Tensilica Patent Information

Tensilica’s robust and rapidly expanding portfolio of United States and international patents covers many of the fundamental concepts of processor design automation, processor configurability, and processor instruction set extensibility. Tensilica’s key patents cover the creation of both hardware and software components of a processor technology solution. Tensilica’s patent portfolio is a key asset for the company as we empower our licensees to build value-added SOCs and systems based on our technology.

US Patents

Sample of U.S. Portfolio, July 2008

Highlights of the patent portfolio include:

US’633
This patent describes some key advances in instruction set design. In particular, it covers architecture characteristics needed for a rich instruction set encoded in a tight encoding space. Encoding using multiple instruction lengths, with free intermixing of instruction lengths delivers significant code size savings compared to traditional RISC cores. Tensilica’s Xtensa instruction set architecture implements these patented concepts in a mixed 24 bit / 16 bit ISA, delivering high performance with dramatic code density improvements compared to older fixed architecture 32 bit RISC processors.

US ‘683
This fundamental patent describes the core concept of processor creation from a configuration specification. Seamless generation of hardware and software is the key to making configured or extended processors useful. Automation frees the user from the tedium of implementation of concepts and focuses architects on fully exploring the available design space in order to achieve a global solution optimization. Automatic generation of hardware and software also dramatically speeds up design cycles, since all the elements of an optimized, application-specific processor solution are guaranteed to be correct by construction

US’515
Rapid evaluation of target instruction extensions is a key productivity enabler in the use of configurable processors. This patent describes the rapid evaluation of processor extensions by enabling users to quickly adapt software development tools to incorporate new extensions. Users of Tensilica’s technology interact with a powerful graphical user interface – the Xtensa Xplorer design environment – that presents numerous visualization and automation techniques to further enhance user productivity during the processor configuration process.

US’697
Language-based processor extension is another key enabler for configurable processor technology. A processor description, including new operations and new programmer state is essential to generation of new instruction hardware and support of new instructions by software development tools. Tensilica’s TIE language (Tensilica Instruction Extension) embodies these ideas, providing a means to quickly specify new instructions, new registers, new processor state, and new processor I/Os.

US’327
Robust software tool and operating system support is the key to the success of any processor architecture – whether configurable or older fixed architectures. This patent describes fundamental methods for automatic adaptation of operating systems and other software to configured processors. Every Tensilica processor is delivered with a complete and robust software development tool environment, including fast simulators and system models. And the Tensilica architecture is supported by a rich and growing ecosystem of third party tool suppliers, including numerous operating systems partners.

US’548
Automatic discovery of processor instruction set extensions by source code analysis is a basic breakthrough in processor design. The technology covered by this patent allows users without processor design experience to generate powerful and flexible new instruction sets even without experience or knowledge of instruction set design basics. Tensilica’s XPRES Compiler embodies these concepts. XPRES Compiler analyses C and C++ source code and generates a series of suggested optimal processor configurations for that target application workload.

US’735
This fundamental patent covers the basic idea of building processors where a standard base configuration is combined with a rapidly-designed portion implementing any desired instruction extensions. It covers methods such as extending a processor via added instructions implemented in reprogrammable logic. This concept enables real-time configuration of processor instruction sets in field deployed silicon, and the combination of high-speed base processor pipelines with fast-time-to-market processor extensions.

International Patents

Sample of International Portfolio, July 2008