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The DPU Story
Cadence's Tensilica processor cores excel in the SOC dataplane. That's where the hardest data-intensive work must be done to create the low-power, high-speed electronic devices consumers want today. We call these cores DPUs (dataplane processing units).
Why Cadence
Only Cadence has a processor architecture and Cloud-based automated design system that was designed, from the start, to be efficiently customized for the complex signal-intensive dataplane processing tasks. That’s why almost 200 companies have chosen Tensilica DPUs for their chip designs in everything from smart phones to computer systems and peripherals to network infrastructure equipment and more.
DPU Benefits
Because they're optimized for the power, performance, and area requirements, DPUs deliver 10-100x more performance than standard CPUs and DSPs. Other benefits include:
- Easy customization with our patented automated tools.
- Product differentiation – each DPU can be unique, making it almost impossible to copy.
- Reduced time to market – dramatically less verification time.
- Flexibility – Because it's programmable you can make changes after tape-out.
In the Spotlight
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Apple iMAC
The iMac relies on AMD’s Radeon HD graphics processor, which uses Tensilica’s DPUs to accelerate the video stream decoding for incredible HD videos and an immersive gaming experience.
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Samsung Galaxy S® III
The Samsung Galaxy S® III and other smartphones use Tensilica DPUs for intelligent voice processing.
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Samsung TVs and Blu-Ray Disc Players
Samsung is using Tensilica’s HiFi Audio DSPs for outstanding voice and audio quality in its digital TVs and Blu-Ray Disc players.
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Amazon Kindle
The Amazon Kindle uses a Tensilica DPU for its WiFi connection.
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Sharp Aquos SH-10D
The Sharp Aquos SH-10D and many other phones that use NTT Docomo’s LTE network in Japan use Tensilica’s DPUs for the LTE radio.
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Huawei Ascend P2
Huawei uses Tensilica DPUs for voice, noise reduction, and LTE in the Ascend P2, the world’s fastest LTE smartphone.
News
Events
Austin Convention Center, Austin, Texas USA, Cadence Booth 2214
Tuesday, June 4, 2013, 10:30 - 12:00, room 12AB, Austin, Texas
Cadence Fellow Chris Rowen will present "Goldilocks and the Three Bears of Programmability"
July 15-19, 2013 - Otsu, Japan
Cadence Fellow Chris Rowen will present "Grand Challenge Scaling - Pushing a Fully Programmable TeraOp into Handset Imaging" Session 11, Wednesday, July 17
